diff_io_top.tan.rpt

altera FPGA/CPLD高级篇(VHDL源代码)

+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1S10F780C6       ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Maximum Strongly Connected Component loop size        ; 50                 ;      ;    ;
; Number of source nodes to report per destination node ; 500                ;      ;    ;
; Number of destination nodes to report                 ; 500                ;      ;    ;
; Number of paths to report                             ; 500                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;
; Include external pin delays in fmax calculations      ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------+----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------------+--------------+
; Type                                                                            ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                              ; To                                                                 ; From Clock                                                       ; To Clock                                                         ; Failed Paths ;
+---------------------------------------------------------------------------------+----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------------+--------------+
; Clock Setup: 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock' ; 5.994 ns ; 105.01 MHz ( period = 9.523 ns ) ; 283.37 MHz ( period = 3.529 ns ) ; mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT15 ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14]     ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; 0            ;
; Clock Setup: 'lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1' ; 7.287 ns ; 105.01 MHz ( period = 9.523 ns ) ; N/A                              ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13]                                    ; lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]~in5 ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1 ; 0            ;
; Total number of failed paths                                                    ;          ;                                  ;                                  ;                                                                                                   ;                                                                    ;                                                                  ;                                                                  ; 0            ;
+---------------------------------------------------------------------------------+----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------+--------------------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                      ;