fir_top_sim.v

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· Verilog 代码 · 共 26 行

module fir_top(	 clock,
			 rst,
			 data_in,
			 fir_result,
			 done,
			 rdy_to_ld);
parameter DATA_WIDTH  = 12;
parameter ACCUM_WIDTH = 27;

input clock, rst;
input [DATA_WIDTH-1:0] data_in;
output done, rdy_to_ld;
output [ACCUM_WIDTH-1:0] fir_result;

wire done, rdy_to_ld;
wire [ACCUM_WIDTH-1:0] fir_result;

fir_top_st  UST (.clk(clock),
          .rst(rst),
          .data_in(data_in), 
          .done(done),
          .rdy_to_ld(rdy_to_ld),
          .fir_result(fir_result) );

endmodule