data_buffer.bsf

altera FPGA/CPLD高级篇(VHDL源代码)

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 0 0 160 144)
	(text "data_buffer" (rect 49 1 118 17)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 128 24 140)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "data[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
		(text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
		(line (pt 0 32)(pt 16 32)(line_width 3))
	)
	(port
		(pt 0 56)
		(input)
		(text "wrreq" (rect 0 0 33 14)(font "Arial" (font_size 8)))
		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
		(line (pt 0 56)(pt 16 56)(line_width 1))
	)
	(port
		(pt 0 72)
		(input)
		(text "rdreq" (rect 0 0 28 14)(font "Arial" (font_size 8)))
		(text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
		(line (pt 0 72)(pt 16 72)(line_width 1))
	)
	(port
		(pt 0 96)
		(input)
		(text "clock" (rect 0 0 27 14)(font "Arial" (font_size 8)))
		(text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
		(line (pt 0 96)(pt 16 96)(line_width 1))
	)
	(port
		(pt 160 32)
		(output)
		(text "q[7..0]" (rect 0 0 33 14)(font "Arial" (font_size 8)))
		(text "q[7..0]" (rect 111 26 141 39)(font "Arial" (font_size 8)))
		(line (pt 160 32)(pt 144 32)(line_width 3))
	)
	(port
		(pt 160 56)
		(output)
		(text "full" (rect 0 0 15 14)(font "Arial" (font_size 8)))
		(text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
		(line (pt 160 56)(pt 144 56)(line_width 1))
	)
	(port
		(pt 160 72)
		(output)
		(text "empty" (rect 0 0 31 14)(font "Arial" (font_size 8)))
		(text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8)))
		(line (pt 160 72)(pt 144 72)(line_width 1))
	)
	(drawing
		(text "8 bits x 8192 words" (rect 63 116 144 128)(font "Arial" ))
		(line (pt 16 16)(pt 144 16)(line_width 1))
		(line (pt 144 16)(pt 144 128)(line_width 1))
		(line (pt 144 128)(pt 16 128)(line_width 1))
		(line (pt 16 128)(pt 16 16)(line_width 1))
		(line (pt 16 108)(pt 144 108)(line_width 1))
		(line (pt 16 90)(pt 22 96)(line_width 1))
		(line (pt 22 96)(pt 16 102)(line_width 1))
	)
)