opcodes_small.h

270的linux说明

/*

Copyright (c) 2008, Intel Corporation. 

All rights reserved.

 

Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:


    * Redistributions of source code must retain the above copyright notice, 
this list of conditions and the following disclaimer.

    * Redistributions in binary form must reproduce the above copyright notice, 
this list of conditions and the following disclaimer in the documentation and/or 
other materials provided with the distribution.

    * Neither the name of Intel Corporation nor the names of its contributors 
may be used to endorse or promote products derived from this software without 
specific prior written permission.

 

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.

*/

// Version 1.5


// PNI stuff

#ifndef _TNI_OPCODES_
#define _TNI_OPCODES_


// PNI
#define xmm_lddqu __asm _emit 0xF2 __asm _emit 0x0F __asm _emit 0xF0 
#define xmm_haddps __asm _emit 0xF2 __asm _emit 0x0F __asm _emit 0x7C

#define rxmm0 0x00
#define	rxmm1 0x01
#define	rxmm2 0x02
#define	rxmm3 0x03
#define	rxmm4 0x04
#define	rxmm5 0x05
#define	rxmm6 0x06
#define	rxmm7 0x07
#define	rxmm8 0x08

#define r_eax 0x00
#define r_ebx 0x03
#define r_ecx 0x01
#define r_edx 0x02
#define r_esi 0x06
#define r_edi 0x07
#define r_ebp 0x05
#define r_esp 0x04
#define r_none 0x04

#define m_eax 0x00
#define m_ebx 0x03
#define m_ecx 0x01
#define m_edx 0x02
#define m_esi 0x06
#define m_edi 0x07
#define m_ebp 0x05
#define m_none 0x04

#define SCALE_1 0x00
#define SCALE_2 0x08
#define SCALE_4 0x10
#define SCALE_8 0x18

#define m_1eax SCALE_1 + m_eax
#define m_1ebx SCALE_1 + m_ecx
#define m_1ecx SCALE_1 + m_edx
#define m_1edx SCALE_1 + m_esi
#define m_1esi SCALE_1 + m_edi
#define m_1ebp SCALE_1 + m_ebp
#define m_2eax SCALE_2 + m_eax
#define m_2ebx SCALE_2 + m_ebx
#define m_2ecx SCALE_2 + m_ecx
#define m_2edx SCALE_2 + m_edx
#define m_2esi SCALE_2 + m_esi
#define m_2edi SCALE_2 + m_edi
#define m_2ebp SCALE_2 + m_ebp
#define m_4eax SCALE_4 + m_eax
#define m_4ebx SCALE_4 + m_ebx
#define m_4ecx SCALE_4 + m_ecx
#define m_4edx SCALE_4 + m_edx
#define m_4esi SCALE_4 + m_esi
#define m_4edi SCALE_4 + m_edi
#define m_4ebp SCALE_4 + m_ebp
#define m_8eax SCALE_8 + m_eax
#define m_8ebx SCALE_8 + m_ebx
#define m_8ecx SCALE_8 + m_ecx
#define m_8edx SCALE_8 + m_edx
#define m_8esi SCALE_8 + m_esi
#define m_8edi SCALE_8 + m_edi
#define m_8ebp SCALE_8 + m_ebp

// reg reg.  example:  pshufb xmm1, xmm2
#define normal_r_r( opc, DST, SRC) opc __asm _emit (0xc0 + DST*8 + SRC)
// Load forms
// reg mem32  example:  pshufb xmm1, xmmword ptr (my_global_value)
//#define normal_r_md(opc, X, YB0, YB1, YB2, YB3 ) opc __asm _emit (0x00 + X*8 + 0x05) __asm _emit YB3 __asm _emit YB2 __asm _emit YB1 __asm _emit YB0
#define normal_r_md(opc, DEST, DISP32) opc __asm _emit (0x00 + DEST*8 + 0x05) __asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF)
// reg [r32]  example:  pshufb xmm1, xmmword ptr [eax]
#define normal_r_mb(opc,  DEST, BASE ) opc __asm _emit (0x00 + DEST*8 + BASE)
// reg [r32 + index] example: pshufb xmm1, xmmword ptr [eax + 0x10]
#define normal_r_mbd(opc,  DEST, BASE, DISP32) opc __asm _emit (0x80 + DEST*8 + BASE) __asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF)
// reg [r32 + n*r32 + index] example: pshufb xmm1, xmmword ptr [eax + 4*ebx + 0x10]
#define normal_r_mbsid(opc, DEST, BASE, SCALE, INDEX, DISP32) opc __asm _emit (0x80 + DEST*8 + m_none) __asm _emit (8*(SCALE+INDEX)+BASE)__asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF)
#define normal_r_mb8d(opc, DST, BASE, DISP8) opc __asm _emit (0x40 + DST*8 + m_none) __asm _emit (8*(m_none)+BASE) __asm _emit (DISP8)

#define normal_r_imm32(opc,X,IMM32) opc __asm _emit (0xc0 + X*8) __asm _emit (IMM32&0xFF) __asm _emit ((IMM32>>8)&0xFF) __asm _emit ((IMM32>>16)&0xFF) __asm _emit ((IMM32>>24)&0xFF)

// reg [r32 + scale*r32+index]

// Store forms
// reg mem32  example:  pshufb xmm1, xmmword ptr (my_global_value)
//#define normal_md_r(opc, SRC, DISP32) opc __asm _emit (0x00 + SRC*8 + 0x05) __asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF)
// reg [r32]  example:  pshufb xmm1, xmmword ptr [eax]
//#define normal_mb_r(opc, SRC, BASE) opc __asm _emit (0x00 + SRC*8 + BASE)
// reg [r32 + index] example: pshufb xmm1, xmmword ptr [eax + 0x10]
//#define normal_mbd_r(opc,  SRC, BASE, DISP32) opc __asm _emit (0x80 + SRC*8 + BASE) __asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF)
// reg [r32 + n*r32 + index] example: pshufb xmm1, xmmword ptr [eax + 4*ebx + 0x10]
//#define normal_mbsid_r(opc, SRC,BASE,SCALE,INDEX,DISP32) opc __asm _emit (0x80 + SRC*8 + m_none) __asm _emit (8*(INDEX+SCALE)+BASE)__asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF)


// reg reg.  example:  pshufb xmm1, xmm2
#define imm_r_r( opc, DEST, SRC, IMM8) opc __asm _emit (0xc0 + DEST*8 + SRC) __asm _emit IMM8
// reg mem32  example:  pshufb xmm1, xmmword ptr (my_global_value)
#define imm_r_md(opc, DEST, DISP32, IMM8) opc __asm _emit (0x00 + DEST*8 + 0x05) __asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF) __asm _emit IMM8
// reg [r32]  example:  pshufb xmm1, xmmword ptr [eax]
#define imm_r_mb(opc,  DEST, BASE, IMM8) opc __asm _emit (0x00 + DEST*8 + BASE) __asm _emit imm
// reg [r32 + index] example: pshufb xmm1, xmmword ptr [eax + 0x10]
#define imm_r_mbd(opc,  DEST, BASE, DISP32, IMM8) opc __asm _emit (0x80 + DEST*8 + BASE) __asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF) __asm _emit IMM8
// reg [r32 + n*r32 + index] example: pshufb xmm1, xmmword ptr [eax + 4*ebx + 0x10]
#define imm_r_mbsid(opc, DEST, BASE, SCALE, INDEX, DISP32, IMM8) opc __asm _emit (0x80 + DEST*8 + m_none) __asm _emit (8*(SCALE+INDEX)+BASE) __asm _emit (DISP32&0xFF) __asm _emit ((DISP32>>8)&0xFF) __asm _emit ((DISP32>>16)&0xFF) __asm _emit ((DISP32>>24)&0xFF) __asm _emit IMM8


// XMM versions.

// LDDQU
#define lddqu_r_mb(DEST,BASE)						normal_r_mb(xmm_lddqu,DEST,BASE)
#define lddqu_r_mbsid(DEST,BASE,SCALE, INDEX, DISP32) normal_r_mbsid(xmm_lddqu,DEST,BASE,SCALE, INDEX, DISP32)

// HADDPS
#define haddps_r_r(X,Y)						normal_r_r(xmm_haddps,X,Y)

#endif /*_TNI_OPCODES_ */