📄 440cpu.h

📁 qnx powerpc MPC8245的 BSP源文件
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#define PPC440_UIC1_XR_MSI3		_ONEBIT32B(8)#define PPC440_UIC1_XR_MSI4		_ONEBIT32B(9)#define PPC440_UIC1_XR_MSI5		_ONEBIT32B(10)#define PPC440_UIC1_XR_MSI6		_ONEBIT32B(11)#define PPC440_UIC1_XR_MSI7		_ONEBIT32B(12)#define PPC440_UIC1_XR_MSI8		_ONEBIT32B(13)#define PPC440_UIC1_XR_MSI9		_ONEBIT32B(14)#define PPC440_UIC1_XR_MSI10	_ONEBIT32B(15)#define PPC440_UIC1_XR_MSI11	_ONEBIT32B(16)#define PPC440_UIC1_XR_PPM		_ONEBIT32B(17)#define PPC440_UIC1_XR_EIR7		_ONEBIT32B(18)#define PPC440_UIC1_XR_EIR8		_ONEBIT32B(19)#define PPC440_UIC1_XR_EIR9		_ONEBIT32B(20)#define PPC440_UIC1_XR_EIR10	_ONEBIT32B(21)#define PPC440_UIC1_XR_EIR11	_ONEBIT32B(22)#define PPC440_UIC1_XR_EIR12	_ONEBIT32B(23)#define PPC440_UIC1_XR_SRE		_ONEBIT32B(24)#define PPC440_UIC1_XR_PAE		_ONEBIT32B(27)#define PPC440_UIC1_XR_ETH0		_ONEBIT32B(28)#define PPC440_UIC1_XR_EWU0		_ONEBIT32B(29)#define PPC440_UIC1_XR_ETH1		_ONEBIT32B(30)#define PPC440_UIC1_XR_EWU1		_ONEBIT32B(31)#define PPC440GP_CPC0_SYS0_TUNE_MASK	_BITFIELD32B(9, 0x3ff)#define PPC440GP_CPC0_SYS0_TUNE_SHIFT	(31-9)#define PPC440GP_CPC0_SYS0_FBDV_MASK	_BITFIELD32B(13, 0xf)#define PPC440GP_CPC0_SYS0_FBDV_SHIFT	(31-13)#define PPC440GP_CPC0_SYS0_FWDVA_MASK	_BITFIELD32B(16, 0x7)#define PPC440GP_CPC0_SYS0_FWDVA_SHIFT	(31-16)#define PPC440GP_CPC0_SYS0_FWDVB_MASK	_BITFIELD32B(19, 0x7)#define PPC440GP_CPC0_SYS0_FWDVB_SHIFT	(31-19)#define PPC440GP_CPC0_SYS0_OPDV_MASK	_BITFIELD32B(21, 0x3)#define PPC440GP_CPC0_SYS0_OPDV_SHIFT	(31-21)#define PPC440GP_CPC0_SYS0_EPDV_MASK	_BITFIELD32B(23, 0x3)#define PPC440GP_CPC0_SYS0_EPDV_SHIFT	(31-23)#define PPC440GP_CPC0_SYS0_EXTSL		_ONEBIT32B(24)#define PPC440GP_CPC0_SYS0_RW_MASK		_BITFIELD32B(26, 0x3)#define PPC440GP_CPC0_SYS0_RW_SHIFT		(31-26)#define PPC440GP_CPC0_SYS0_RW_8			_BITFIELD32B(26, 0x0)#define PPC440GP_CPC0_SYS0_RW_16		_BITFIELD32B(26, 0x1)#define PPC440GP_CPC0_SYS0_RW_32		_BITFIELD32B(26, 0x3)#define PPC440GP_CPC0_SYS0_RL			_ONEBIT32B(27)#define PPC440GP_CPC0_SYS0_ZMIISL_MASK	_BITFIELD32B(29, 0x3)#define PPC440GP_CPC0_SYS0_ZMIISL_SHIFT	(31-29)#define PPC440GP_CPC0_SYS0_ZMIISL_MII		_BITFIELD32B(29, 0x0)#define PPC440GP_CPC0_SYS0_ZMIISL_SMII		_BITFIELD32B(29, 0x1)#define PPC440GP_CPC0_SYS0_ZMIISL_ZMII10	_BITFIELD32B(29, 0x2)#define PPC440GP_CPC0_SYS0_ZMIISL_ZMII100	_BITFIELD32B(29, 0x3)#define PPC440GP_CPC0_SYS0_BYPASS		_ONEBIT32B(30)#define PPC440GP_CPC0_SYS0_Nto1			_ONEBIT32B(31)#define PPC440GP_CPC0_SYS1_TUNE_MASK	_BITFIELD32B(9, 0x3ff)#define PPC440GP_CPC0_SYS1_TUNE_SHIFT	(31-9)#define PPC440GP_CPC0_SYS1_BYPASS		_ONEBIT32B(10)#define PPC440GP_CPC0_SYS1_PAE			_ONEBIT32B(11)#define PPC440GP_CPC0_SYS1_PHCE			_ONEBIT32B(12)#define PPC440GP_CPC0_SYS1_PISE			_ONEBIT32B(13)#define PPC440GP_CPC0_SYS1_PCWE			_ONEBIT32B(14)#define PPC440GP_CPC0_SYS1_PPIM_MASK	_BITFIELD32B(18, 0xf)#define PPC440GP_CPC0_SYS1_PPIM_SHIFT	(31-18)#define PPC440GP_CPC0_SYS1_PR64E		_ONEBIT32B(19)#define PPC440GP_CPC0_SYS1_PXFS_MASK	_BITFIELD32B(21, 0x3)#define PPC440GP_CPC0_SYS1_PXFS_SHIFT	(31-21)#define PPC440GP_CPC0_SYS1_PXFS_100_133MHZ	_BITFIELD32B(21, 0x0)#define PPC440GP_CPC0_SYS1_PXFS_66_100MHZ	_BITFIELD32B(21, 0x1)#define PPC440GP_CPC0_SYS1_PXFS_50_66MHZ	_BITFIELD32B(21, 0x2)#define PPC440GP_CPC0_SYS1_PQXDE		_ONEBIT32B(22)#define PPC440GP_CPC0_SYS1_PDM			_ONEBIT32B(24)#define PPC440GP_CPC0_SYS1_TUNEEN		_ONEBIT32B(25)/* * SPR values */#define PPC440_SPR_CCR0			0x3b3#define PPC440_SPR_CCR1			0x378#define PPC440_SPR_DCDBTRH		0x39d#define PPC440_SPR_DCDBTRL		0x39c#define PPC440_SPR_DNV(x)		(0x390+(x))#define PPC440_SPR_DTV(x)		(0x394+(x))#define PPC440_SPR_DVC1			0x13e#define PPC440_SPR_DVC2			0x13f#define PPC440_SPR_DVLIM		0x398#define PPC440_SPR_ICDBDR		0x3d3#define PPC440_SPR_ICDBTRH		0x39f#define PPC440_SPR_ICDBTRL		0x39e#define PPC440_SPR_INV(x)		(0x370+(x))#define PPC440_SPR_ITV(x)		(0x374+(x))#define PPC440_SPR_IVLIM		0x399#define PPC440_SPR_MMUCR		0x3b2#define PPC440_SPR_RSTCFG		0x39b#define PPC440_SPR_USPR0		0x100#define PPC440GX_SPR_MCSRR0		0x23a#define PPC440GX_SPR_MCSRR1		0x23b/* * SDR Register Definations  */#define	PPC440GX_SDR0_CFG_ADDR	0x000e#define	PPC440GX_SDR0_CFG_DATA	0x000f#define	PPC440GX_SDR0_SDSTP0	0x0020#define	PPC440GX_SDR0_SDSTP1	0x0021#define	PPC440GX_SDR0_UART0		0x0120#define	PPC440GX_SDR0_UART1		0x0121#define	PPC440GX_SDR0_MFR		0x4300#define	set_sdr(reg, data)		set_dcr(PPC440GX_SDR0_CFG_ADDR,reg);set_dcr(PPC440GX_SDR0_CFG_DATA,data);#define	get_sdr(reg, data)		set_dcr(PPC440GX_SDR0_CFG_ADDR,reg);data = get_dcr(PPC440GX_SDR0_CFG_DATA);/* * SDR register bits */#define PPC440GX_SDR0_SDSTP0_ENG_MAKS		_ONEBIT32B(0)#define PPC440GX_SDR0_SDSTP0_ENG_SHIFT		(31-0)#define PPC440GX_SDR0_SDSTP0_SRC_MASK		_ONEBIT32B(1)#define PPC440GX_SDR0_SDSTP0_SRC_SHIFT		(31-1)#define PPC440GX_SDR0_SDSTP0_SEL_MASK		_BITFIELD32B(4, 0x7)#define PPC440GX_SDR0_SDSTP0_SEL_SHIFT		(31-4)#define PPC440GX_SDR0_SDSTP0_FBDV_MASK		_BITFIELD32B(19, 0x1f)#define PPC440GX_SDR0_SDSTP0_FBDV_SHIFT		(31-19)#define PPC440GX_SDR0_SDSTP0_FWDVA_MASK		_BITFIELD32B(23, 0xf)#define PPC440GX_SDR0_SDSTP0_FWDVA_SHIFT	(31-23)#define PPC440GX_SDR0_SDSTP0_FWDVB_MASK		_BITFIELD32B(26, 0x7)#define PPC440GX_SDR0_SDSTP0_FWDVB_SHIFT	(31-26)#define PPC440GX_SDR0_SDSTP0_PRBDV0_MASK	_BITFIELD32B(29, 0x7)#define PPC440GX_SDR0_SDSTP0_PRBDV0_SHIFT	(31-29)#define PPC440GX_SDR0_SDSTP0_OPBDV0_MASK	_BITFIELD32B(31, 0x3)#define PPC440GX_SDR0_SDSTP0_OPBDV0_SHIFT	(31-31)#define PPC440GX_SDR0_SDSTP1_LFBDV_MASK		_BITFIELD32B(5, 0x3f)#define PPC440GX_SDR0_SDSTP1_LFBDV_SHIFT	(31-5)#define PPC440GX_SDR0_SDSTP1_PERDV0_MASK	_BITFIELD32B(7, 0x3)#define PPC440GX_SDR0_SDSTP1_PERDV0_SHIFT	(31-7)/* * DCR values */#define PPC440_DCR_EBC0_CFGADDR	0x012#define PPC440_DCR_EBC0_CFGDATA	0x013#define PPC440_DCRBASE_UIC0		0x0c0#define PPC440_DCRBASE_UIC1		0x0d0/* on 440GX */#define PPC440_DCRBASE_UIC2		0x210#define PPC440_DCRBASE_UICB0	0x200#define PPC440_DCR_UIC0_SR		PPCIBM_DCR_UIC_SR(PPC440_DCRBASE_UIC0)#define PPC440_DCR_UIC0_ER		PPCIBM_DCR_UIC_ER(PPC440_DCRBASE_UIC0)#define PPC440_DCR_UIC0_CR		PPCIBM_DCR_UIC_CR(PPC440_DCRBASE_UIC0)#define PPC440_DCR_UIC0_PR		PPCIBM_DCR_UIC_PR(PPC440_DCRBASE_UIC0)#define PPC440_DCR_UIC0_TR		PPCIBM_DCR_UIC_TR(PPC440_DCRBASE_UIC0)#define PPC440_DCR_UIC0_MSR		PPCIBM_DCR_UIC_MSR(PPC440_DCRBASE_UIC0)#define PPC440_DCR_UIC0_VCR		PPCIBM_DCR_UIC_VCR(PPC440_DCRBASE_UIC0)#define PPC440_DCR_UIC0_VR		PPCIBM_DCR_UIC_VR(PPC440_DCRBASE_UIC0)#define PPC440_DCR_UIC1_SR		PPCIBM_DCR_UIC_SR(PPC440_DCRBASE_UIC1)#define PPC440_DCR_UIC1_ER		PPCIBM_DCR_UIC_ER(PPC440_DCRBASE_UIC1)#define PPC440_DCR_UIC1_CR		PPCIBM_DCR_UIC_CR(PPC440_DCRBASE_UIC1)#define PPC440_DCR_UIC1_PR		PPCIBM_DCR_UIC_PR(PPC440_DCRBASE_UIC1)#define PPC440_DCR_UIC1_TR		PPCIBM_DCR_UIC_TR(PPC440_DCRBASE_UIC1)#define PPC440_DCR_UIC1_MSR		PPCIBM_DCR_UIC_MSR(PPC440_DCRBASE_UIC1)#define PPC440_DCR_UIC1_VCR		PPCIBM_DCR_UIC_VCR(PPC440_DCRBASE_UIC1)#define PPC440_DCR_UIC1_VR		PPCIBM_DCR_UIC_VR(PPC440_DCRBASE_UIC1)#define PPC440_DCR_UIC2_SR		PPCIBM_DCR_UIC_SR(PPC440_DCRBASE_UIC2)#define PPC440_DCR_UIC2_ER		PPCIBM_DCR_UIC_ER(PPC440_DCRBASE_UIC2)#define PPC440_DCR_UIC2_CR		PPCIBM_DCR_UIC_CR(PPC440_DCRBASE_UIC2)#define PPC440_DCR_UIC2_PR		PPCIBM_DCR_UIC_PR(PPC440_DCRBASE_UIC2)#define PPC440_DCR_UIC2_TR		PPCIBM_DCR_UIC_TR(PPC440_DCRBASE_UIC2)#define PPC440_DCR_UIC2_MSR		PPCIBM_DCR_UIC_MSR(PPC440_DCRBASE_UIC2)#define PPC440_DCR_UIC2_VCR		PPCIBM_DCR_UIC_VCR(PPC440_DCRBASE_UIC2)#define PPC440_DCR_UIC2_VR		PPCIBM_DCR_UIC_VR(PPC440_DCRBASE_UIC2)#define PPC440_DCR_UICB0_SR		PPCIBM_DCR_UIC_SR(PPC440_DCRBASE_UICB0)#define PPC440_DCR_UICB0_ER		PPCIBM_DCR_UIC_ER(PPC440_DCRBASE_UICB0)#define PPC440_DCR_UICB0_CR		PPCIBM_DCR_UIC_CR(PPC440_DCRBASE_UICB0)#define PPC440_DCR_UICB0_PR		PPCIBM_DCR_UIC_PR(PPC440_DCRBASE_UICB0)#define PPC440_DCR_UICB0_TR		PPCIBM_DCR_UIC_TR(PPC440_DCRBASE_UICB0)#define PPC440_DCR_UICB0_MSR	PPCIBM_DCR_UIC_MSR(PPC440_DCRBASE_UICB0)#define PPC440_DCR_UICB0_VCR	PPCIBM_DCR_UIC_VCR(PPC440_DCRBASE_UICB0)#define PPC440_DCR_UICB0_VR		PPCIBM_DCR_UIC_VR(PPC440_DCRBASE_UICB0)#define	PPC440_DCR_CPC0_SYS0	0xe0#define	PPC440_DCR_CPC0_SYS1	0xe1#define	PPC440_DCR_CPC0_CUST0	0xe2#define	PPC440_DCR_CPC0_CUST1	0xe3#define	PPC440_DCR_CPC0_STRP0	0xe4#define	PPC440_DCR_CPC0_STRP1	0xe5#define	PPC440_DCR_CPC0_STRP2	0xe6#define	PPC440_DCR_CPC0_STRP3	0xe7#define	PPC440_DCR_CPC0_GPIO	0xe8#define PPC440_DCR_CPC0_PLB		0xe9#define	PPC440_DCR_CPC0_CR1		0xea#define	PPC440_DCR_CPC0_CR0		0xeb#define	PPC440_DCR_CPC0_MIRQ0	0xec#define PPC440_DCR_CPC0_MIRQ1	0xed#define	PPC440_DCR_CPC0_RST		0xee#define	PPC440_DCR_CPC0_JTAGID	0xef#define	PPC440GP_DCR_CPC0_SYS0	PPC440_DCR_CPC0_SYS0#define	PPC440GP_DCR_CPC0_SYS1	PPC440_DCR_CPC0_SYS1#define	PPC440GP_DCR_CPC0_CUST0	PPC440_DCR_CPC0_CUST0#define	PPC440GP_DCR_CPC0_CUST1	PPC440_DCR_CPC0_CUST1#define	PPC440GP_DCR_CPC0_STRP0	PPC440_DCR_CPC0_STRP0#define	PPC440GP_DCR_CPC0_STRP1	PPC440_DCR_CPC0_STRP1#define	PPC440GP_DCR_CPC0_STRP2	PPC440_DCR_CPC0_STRP2#define	PPC440GP_DCR_CPC0_STRP3	PPC440_DCR_CPC0_STRP3 	/* * CPC0 Control Register 0 defination */#define	PPC440_CPC0_CR0_SWE		_ONEBIT32B(0)#define	PPC440_CPC0_CR0_CETE	_ONEBIT32B(1)#define	PPC440_CPC0_CR0_U1FCS	_ONEBIT32B(2)#define	PPC440_CPC0_CR0_U0DTE	_ONEBIT32B(3)#define	PPC440_CPC0_CR0_U0DRE	_ONEBIT32B(4)#define	PPC440_CPC0_CR0_U0DC	_ONEBIT32B(5)#define	PPC440_CPC0_CR0_U1DTE	_ONEBIT32B(6)#define	PPC440_CPC0_CR0_U1DRE	_ONEBIT32B(7)#define	PPC440_CPC0_CR0_U1DC	_ONEBIT32B(8)#define	PPC440_CPC0_CR0_U0EC	_ONEBIT32B(9)#define	PPC440_CPC0_CR0_U1EC	_ONEBIT32B(10)/* * Indirect via EBC0_CFGADDR/EBC0_CFGDATA registers */#define PPC440_EBC0_B0CR		0x00#define PPC440_EBC0_B1CR		0x01#define PPC440_EBC0_B2CR		0x02#define PPC440_EBC0_B3CR		0x03#define PPC440_EBC0_B4CR		0x04#define PPC440_EBC0_B5CR		0x05#define PPC440_EBC0_B6CR		0x06#define PPC440_EBC0_B7CR		0x07#define PPC440_EBC0_B0AP		0x10#define PPC440_EBC0_B1AP		0x11#define PPC440_EBC0_B2AP		0x12#define PPC440_EBC0_B3AP		0x13#define PPC440_EBC0_B4AP		0x14#define PPC440_EBC0_B5AP		0x15#define PPC440_EBC0_B6AP		0x16#define PPC440_EBC0_B7AP		0x17#define PPC440_EBC0_BEAR		0x20#define PPC440_EBC0_BESR		0x21#define PPC440_EBC0_CFG			0x23#define PPC440_EBC0_CID			0x24#endif/* __SRCVERSION("$IQ: 440cpu.h,v 1.8.2.3 $"); */
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