440cpu.h

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


/*
 *  ppc/440cpu.h
 *
 * Registers specific to the 440 chip
 *

 */

#ifndef __PPC_440CPU_H_INCLUDED
#define __PPC_440CPU_H_INCLUDED

#ifndef __PLATFORM_H_INCLUDED
#include <sys/platform.h>
#endif

#ifndef __PPC_BOOKECPU_H_INCLUDED
#include _NTO_HDR_(ppc/bookecpu.h)
#endif

#ifndef __PPC_IBMUIC_H_INCLUDED
#include _NTO_HDR_(ppc/ibmuic.h)
#endif

/*
 * Core Configuration Register 0 bits
 */
#define PPC440_CCR0_DSTG		_ONEBIT32B(10)
#define PPC440_CCR0_DAPUIB		_ONEBIT32B(11)
#define PPC440_CCR0_DTB			_ONEBIT32B(16)
#define PPC440_CCR0_GICBT		_ONEBIT32B(17)
#define PPC440_CCR0_GDCBT		_ONEBIT32B(18)
#define PPC440_CCR0_FLSTA		_ONEBIT32B(23)
#define PPC440_CCR0_ICSLC_MASK	_BITFIELD32B(29,0x3)
#define PPC440_CCR0_ICSLC_SHIFT	(31-29)
#define PPC440_CCR0_ICSLT_MASK	_BITFIELD32B(31,0x3)
#define PPC440_CCR0_ICSLT_SHIFT	(31-31)

/*
 * Core Configuration Register 1 bits
 */
#define PPC440_CCR1_TCS			_ONEBIT32B(24)


/*
 * Data Cache Debug Tag Register High
 */
#define PPC440_DCDBTRH_TRA_MASK		_BITFIELD32B(23,0xffffff)
#define PPC440_DCDBTRH_TRA_SHIFT	(31-23)
#define PPC440_DCDBTRH_V			_ONEBIT32B(24)
#define PPC440_DCDBTRH_TERA_MASK	_BITFIELD32B(31,0xf)
#define PPC440_DCDBTRH_TERA_SHIFT	(31-31)

/*
 * Data Cache Debug Tag Register Low
 */
#define PPC440_DCDBTRL_D_MASK		_BITFIELD32B(23,0xf)
#define PPC440_DCDBTRL_D_SHIFT		(31-27)
#define PPC440_DCDBTRL_U0			_ONEBIT32B(28)
#define PPC440_DCDBTRL_U1			_ONEBIT32B(29)
#define PPC440_DCDBTRL_U2			_ONEBIT32B(30)
#define PPC440_DCDBTRL_U3			_ONEBIT32B(31)


/*
 * Data Cache Normal Victim Register (0-3)
 */
#define PPC440_DNV_VNDXA_MASK		_BITFIELD(7,0xff)
#define PPC440_DNV_VNDXA_SHIFT		(31-7)
#define PPC440_DNV_VNDXB_MASK		_BITFIELD(15,0xff)
#define PPC440_DNV_VNDXB_SHIFT		(31-15)
#define PPC440_DNV_VNDXC_MASK		_BITFIELD(23,0xff)
#define PPC440_DNV_VNDXC_SHIFT		(31-23)
#define PPC440_DNV_VNDXD_MASK		_BITFIELD(31,0xff)
#define PPC440_DNV_VNDXD_SHIFT		(31-31)

/*
 * Data Cache Transient Victim Register (0-3)
 */
#define PPC440_DTV_VNDXA_MASK		_BITFIELD(7,0xff)
#define PPC440_DTV_VNDXA_SHIFT		(31-7)
#define PPC440_DTV_VNDXB_MASK		_BITFIELD(15,0xff)
#define PPC440_DTV_VNDXB_SHIFT		(31-15)
#define PPC440_DTV_VNDXC_MASK		_BITFIELD(23,0xff)
#define PPC440_DTV_VNDXC_SHIFT		(31-23)
#define PPC440_DTV_VNDXD_MASK		_BITFIELD(31,0xff)
#define PPC440_DTV_VNDXD_SHIFT		(31-31)


/*
 * Data Cache Victim Limit Register
 */
#define PPC440_DVLIM_TFLOOR_MASK	_BITFIELD32B(9, 0xff)
#define PPC440_DVLIM_TFLOOR_SHIFT	(31-9)
#define PPC440_DVLIM_TCEILING_MASK	_BITFIELD32B(20, 0xff)
#define PPC440_DVLIM_TCEILING_SHIFT	(31-20)
#define PPC440_DVLIM_NFLOOR_MASK	_BITFIELD32B(31, 0xff)
#define PPC440_DVLIM_NFLOOR_SHIFT	(31-31)


/*
 * Instruction Cache Debug Tag Register High
 */
#define PPC440_ICDBTRH_TEA_MASK		_BITFIELD32B(31, 0xffffff)
#define PPC440_ICDBTRH_TEA_SHIFT	(31-23)
#define PPC440_ICDBTRH_V			_ONEBIT32B(24)

/*
 * Instruction Cache Debug Tag Register Low
 */
#define PPC440_ICDBTRL_TS			_ONEBIT32B(22)
#define PPC440_ICDBTRL_TD			_ONEBIT32B(22)
#define PPC440_ICDBTRL_TID_MASK		_BITFIELD32B(31,0xff)
#define PPC440_ICDBTRL_TID_SHIFT	(31-31)

/*
 * Instruction Cache Normal Victim Register (0-3)
 */
#define PPC440_INV_VNDXA_MASK		_BITFIELD(7,0xff)
#define PPC440_INV_VNDXA_SHIFT		(31-7)
#define PPC440_INV_VNDXB_MASK		_BITFIELD(15,0xff)
#define PPC440_INV_VNDXB_SHIFT		(31-15)
#define PPC440_INV_VNDXC_MASK		_BITFIELD(23,0xff)
#define PPC440_INV_VNDXC_SHIFT		(31-23)
#define PPC440_INV_VNDXD_MASK		_BITFIELD(31,0xff)
#define PPC440_INV_VNDXD_SHIFT		(31-31)

/*
 * Instruction Cache Transient Victim Register (0-3)
 */
#define PPC440_ITV_VNDXA_MASK		_BITFIELD(7,0xff)
#define PPC440_ITV_VNDXA_SHIFT		(31-7)
#define PPC440_ITV_VNDXB_MASK		_BITFIELD(15,0xff)
#define PPC440_ITV_VNDXB_SHIFT		(31-15)
#define PPC440_ITV_VNDXC_MASK		_BITFIELD(23,0xff)
#define PPC440_ITV_VNDXC_SHIFT		(31-23)
#define PPC440_ITV_VNDXD_MASK		_BITFIELD(31,0xff)
#define PPC440_ITV_VNDXD_SHIFT		(31-31)


/*
 * Instruction Cache Victim Limit Register
 */
#define PPC440_IVLIM_TFLOOR_MASK	_BITFIELD32B(9, 0xff)
#define PPC440_IVLIM_TFLOOR_SHIFT	(31-9)
#define PPC440_IVLIM_TCEILING_MASK	_BITFIELD32B(20, 0xff)
#define PPC440_IVLIM_TCEILING_SHIFT	(31-20)
#define PPC440_IVLIM_NFLOOR_MASK	_BITFIELD32B(31, 0xff)
#define PPC440_IVLIM_NFLOOR_SHIFT	(31-31)


/*
 * Memory Management Unit Control Register bits
 */
#define PPC440_MMUCR_SWOA		_ONEBIT32B(7)
#define PPC440_MMUCR_U1TE		_ONEBIT32B(9)
#define PPC440_MMUCR_U2SWOAE	_ONEBIT32B(10)
#define PPC440_MMUCR_DULXE		_ONEBIT32B(12)
#define PPC440_MMUCR_IULXE		_ONEBIT32B(13)
#define PPC440_MMUCR_STS_MASK	_ONEBIT32B(15)
#define PPC440_MMUCR_STS_SHIFT	(31-15)
#define PPC440_MMUCR_STID_MASK	_BITFIELD32B(31,0xff)
#define PPC440_MMUCR_STID_SHIFT	(31-31)


/*
 * Reset Configuration Register bits
 */
#define PPC440_RSTCFG_U0		_ONEBIT32B(16)
#define PPC440_RSTCFG_U1		_ONEBIT32B(17)
#define PPC440_RSTCFG_U2		_ONEBIT32B(18)
#define PPC440_RSTCFG_U3		_ONEBIT32B(19)
#define PPC440_RSTCFG_E			_ONEBIT32B(24)
#define PPC440_RSTCFG_ERPN_MASK	_BITFIEL32B(31,0xf)
#define PPC440_RSTCFG_ERPN_SHIFT (31-31)

/*
 * Extra ESR bits
 */
#define PPC440_ESR_MCI			_ONEBIT32B(0)
#define PPC440_ESR_PCRE			_ONEBIT32B(27)
#define PPC440_ESR_PCMP			_ONEBIT32B(28)
#define PPC440_ESR_PCMP			_ONEBIT32B(28)
#define PPC440_ESR_PCRF_MASK	_BITFIELD32B(29,0x7)
#define PPC440_ESR_PCRF_SHIFT	(31-29)
#define PPC440_ESR_PCRF_NONE	_BITFIELD32B(29,0x0)
#define PPC440_ESR_PCRF_TAKEN	_BITFIELD32B(29,0x1)

/*
 * UIC0 register bits
 */
#define PPC440_UIC0_XR_U0		_ONEBIT32B(0)
#define PPC440_UIC0_XR_U1		_ONEBIT32B(1)
#define PPC440_UIC0_XR_IIC0		_ONEBIT32B(2)
#define PPC440_UIC0_XR_IIC1		_ONEBIT32B(3)
#define PPC440_UIC0_XR_PIM		_ONEBIT32B(4)
#define PPC440_UIC0_XR_PCRW		_ONEBIT32B(5)
#define PPC440_UIC0_XR_PPM		_ONEBIT32B(6)
#define PPC440_UIC0_XR_MSI0		_ONEBIT32B(7)
#define PPC440_UIC0_XR_MSI1		_ONEBIT32B(8)
#define PPC440_UIC0_XR_MSI2		_ONEBIT32B(9)
#define PPC440_UIC0_XR_MTE		_ONEBIT32B(10)
#define PPC440_UIC0_XR_MRE		_ONEBIT32B(11)
#define PPC440_UIC0_XR_D0		_ONEBIT32B(12)
#define PPC440_UIC0_XR_D1		_ONEBIT32B(13)
#define PPC440_UIC0_XR_D2		_ONEBIT32B(14)
#define PPC440_UIC0_XR_D3		_ONEBIT32B(15)
#define PPC440_UIC0_XR_CT0		_ONEBIT32B(18)
#define PPC440_UIC0_XR_CT1		_ONEBIT32B(19)
#define PPC440_UIC0_XR_CT2		_ONEBIT32B(20)
#define PPC440_UIC0_XR_CT3		_ONEBIT32B(21)
#define PPC440_UIC0_XR_CT4		_ONEBIT32B(22)
#define PPC440_UIC0_XR_EIR0		_ONEBIT32B(23)
#define PPC440_UIC0_XR_EIR1		_ONEBIT32B(24)
#define PPC440_UIC0_XR_EIR2		_ONEBIT32B(25)
#define PPC440_UIC0_XR_EIR3		_ONEBIT32B(26)
#define PPC440_UIC0_XR_EIR4		_ONEBIT32B(27)
#define PPC440_UIC0_XR_EIR5		_ONEBIT32B(28)
#define PPC440_UIC0_XR_EIR6		_ONEBIT32B(29)
#define PPC440_UIC0_XR_UIC1NC	_ONEBIT32B(30)
#define PPC440_UIC0_XR_UIC1C	_ONEBIT32B(31)

/*
 * UIC1 register bits
 */
#define PPC440_UIC1_XR_MS		_ONEBIT32B(0)
#define PPC440_UIC1_XR_MTDE		_ONEBIT32B(1)
#define PPC440_UIC1_XR_MRDE		_ONEBIT32B(2)
#define PPC440_UIC1_XR_DEUE		_ONEBIT32B(3)
#define PPC440_UIC1_XR_DECE		_ONEBIT32B(4)
#define PPC440_UIC1_XR_EBC0		_ONEBIT32B(5)
#define PPC440_UIC1_XR_EBMI		_ONEBIT32B(6)
#define PPC440_UIC1_XR_OPB		_ONEBIT32B(7)