📄 405cpu.h

📁 qnx powerpc MPC8245的 BSP源文件
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 *//* * (Ethernet) Transmit Mode Register 0NYI: *//* * (Ethernet) Transmit Mode Register 1NYI: *//* * (Ethernet) Transmit Request Threshold RegisterNYI: *//* * External Peripheral Control RegisterNYI: *//* * PLB-to-OPB Error Status Register 0NYI: *//* * PLB-to-OPB Error Status Register 1NYI: *//* * Instruction Cache Debug Data RegisterNYI: *//* * IIC0 Control RegisterNYI: *//* * IIC0 Direct Control RegisterNYI: *//* * IIC0 Extended Status RegisterNYI: *//* * IIC0 Interrupt Mask RegisterNYI: *//* * IIC0 Mode Control RegisterNYI: *//* * IIC0 Status RegisterNYI: *//* * IIC0 Transfer Count RegisterNYI: *//* * IIC0 Extended Control and Slave Status RegisterNYI: *//* * (Decompression) Address Decode Definition Register 0-1NYI: *//* * (Decompression) Core Configuration RegisterNYI: *//* * (Decompression) Bus Error Status Register 0NYI: *//* * MAL Configuration RegisterNYI: *//* * MAL Error Status RegisterNYI: *//* * MAL Interrupt Enable RegisterNYI: *//* * MAL RX Channel Active Reset RegisterNYI: *//* * MAL RX Channel Active Set RegisterNYI: *//* * MAL Receive Descriptor Interrupt RegisterNYI: *//* * MAL Receive End-of-Buffer Interrupt Status RegisterNYI: *//* * MAL TX Channel Active Reset RegisterNYI: *//* * MAL TX Channel Active Set RegisterNYI: *//* * MAL Transmit Descriptor Interrupt RegisterNYI: *//* * MAL Transmit End-of-Buffer Interrupt Status RegisterNYI: *//* * Memory Bank 0-3 Configuration RegisterNYI: *//* * Memory Controller Options 1 RegisterNYI: *//* * OPB Arbiter Control RegisterNYI: *//* * OPB Arbiter Priority RegisterNYI: *//* * OCM Data-Side Control RegisterNYI: *//* * OCM Instruction-Side Control RegisterNYI: *//* * PLB Arbiter Control RegisterNYI: *//* * Peripheral Bank 0-7 Access Parameters RegisterNYI: *//* * Peripheral Bank 0-7 Configuration RegisterNYI: *//* * Peripheral Bus Error Status Register 0NYI: *//* * Peripheral Bus Error Status Register 1NYI: *//* * PCI Bridge Options Register 1NYI: *//* * PCI Bridge Options Register 2NYI: *//* * PLB Error Status RegisterNYI: *//* * PLB Slave Error Syndrome Register 0NYI: *//* * PLB Slave Error Syndrome Register 1NYI: *//* * PLL Mode RegisterNYI: *//* * PMM 0 Mask/Attribute RegisterNYI: *//* * PMM 1 Mask/Attribute RegisterNYI: *//* * PMM 2 Mask/Attribute RegisterNYI: *//* * Power Management Idle TimerNYI: *//* * Refresh Timer RegisterNYI: *//* * SDRAM Timing Register 1NYI: *//* * Storage Little-Endian Register */#define PPC405_SLER_S0	_ONEBIT32B(0)#define PPC405_SLER_S1	_ONEBIT32B(1)#define PPC405_SLER_S2	_ONEBIT32B(2)#define PPC405_SLER_S3	_ONEBIT32B(3)#define PPC405_SLER_S4	_ONEBIT32B(4)#define PPC405_SLER_S5	_ONEBIT32B(5)#define PPC405_SLER_S6	_ONEBIT32B(6)#define PPC405_SLER_S7	_ONEBIT32B(7)#define PPC405_SLER_S8	_ONEBIT32B(8)#define PPC405_SLER_S9	_ONEBIT32B(9)#define PPC405_SLER_S10	_ONEBIT32B(10)#define PPC405_SLER_S11	_ONEBIT32B(11)#define PPC405_SLER_S12	_ONEBIT32B(12)#define PPC405_SLER_S13	_ONEBIT32B(13)#define PPC405_SLER_S14	_ONEBIT32B(14)#define PPC405_SLER_S15	_ONEBIT32B(15)#define PPC405_SLER_S16	_ONEBIT32B(16)#define PPC405_SLER_S17	_ONEBIT32B(17)#define PPC405_SLER_S18	_ONEBIT32B(18)#define PPC405_SLER_S19	_ONEBIT32B(19)#define PPC405_SLER_S20	_ONEBIT32B(20)#define PPC405_SLER_S21	_ONEBIT32B(21)#define PPC405_SLER_S22	_ONEBIT32B(22)#define PPC405_SLER_S23	_ONEBIT32B(23)#define PPC405_SLER_S24	_ONEBIT32B(24)#define PPC405_SLER_S25	_ONEBIT32B(25)#define PPC405_SLER_S26	_ONEBIT32B(26)#define PPC405_SLER_S27	_ONEBIT32B(27)#define PPC405_SLER_S28	_ONEBIT32B(28)#define PPC405_SLER_S29	_ONEBIT32B(29)#define PPC405_SLER_S30	_ONEBIT32B(30)#define PPC405_SLER_S31	_ONEBIT32B(31)/* * Storage User-Defined 0 Register */#define PPC405_SU0R_S0	_ONEBIT32B(0)#define PPC405_SU0R_S1	_ONEBIT32B(1)#define PPC405_SU0R_S2	_ONEBIT32B(2)#define PPC405_SU0R_S3	_ONEBIT32B(3)#define PPC405_SU0R_S4	_ONEBIT32B(4)#define PPC405_SU0R_S5	_ONEBIT32B(5)#define PPC405_SU0R_S6	_ONEBIT32B(6)#define PPC405_SU0R_S7	_ONEBIT32B(7)#define PPC405_SU0R_S8	_ONEBIT32B(8)#define PPC405_SU0R_S9	_ONEBIT32B(9)#define PPC405_SU0R_S10	_ONEBIT32B(10)#define PPC405_SU0R_S11	_ONEBIT32B(11)#define PPC405_SU0R_S12	_ONEBIT32B(12)#define PPC405_SU0R_S13	_ONEBIT32B(13)#define PPC405_SU0R_S14	_ONEBIT32B(14)#define PPC405_SU0R_S15	_ONEBIT32B(15)#define PPC405_SU0R_S16	_ONEBIT32B(16)#define PPC405_SU0R_S17	_ONEBIT32B(17)#define PPC405_SU0R_S18	_ONEBIT32B(18)#define PPC405_SU0R_S19	_ONEBIT32B(19)#define PPC405_SU0R_S20	_ONEBIT32B(20)#define PPC405_SU0R_S21	_ONEBIT32B(21)#define PPC405_SU0R_S22	_ONEBIT32B(22)#define PPC405_SU0R_S23	_ONEBIT32B(23)#define PPC405_SU0R_S24	_ONEBIT32B(24)#define PPC405_SU0R_S25	_ONEBIT32B(25)#define PPC405_SU0R_S26	_ONEBIT32B(26)#define PPC405_SU0R_S27	_ONEBIT32B(27)#define PPC405_SU0R_S28	_ONEBIT32B(28)#define PPC405_SU0R_S29	_ONEBIT32B(29)#define PPC405_SU0R_S30	_ONEBIT32B(30)#define PPC405_SU0R_S31	_ONEBIT32B(31)/* * UIC Critical Register */#define PPC405_UIC0_CR_U0IC		_ONEBIT32B(0)#define PPC405_UIC0_CR_U1IC		_ONEBIT32B(1)#define PPC405_UIC0_CR_IICIC	_ONEBIT32B(2)#define PPC405_UIC0_CR_EMIC		_ONEBIT32B(3)#define PPC405_UIC0_CR_PCIIC	_ONEBIT32B(4)#define PPC405_UIC0_CR_D0IC		_ONEBIT32B(5)#define PPC405_UIC0_CR_D1IC		_ONEBIT32B(6)#define PPC405_UIC0_CR_D2IC		_ONEBIT32B(7)#define PPC405_UIC0_CR_D3IC		_ONEBIT32B(8)#define PPC405_UIC0_CR_EWIC		_ONEBIT32B(9)#define PPC405_UIC0_CR_MSIC		_ONEBIT32B(10)#define PPC405_UIC0_CR_MTEIC	_ONEBIT32B(11)#define PPC405_UIC0_CR_MREIC	_ONEBIT32B(12)#define PPC405_UIC0_CR_MTDIC	_ONEBIT32B(13)#define PPC405_UIC0_CR_MRDIC	_ONEBIT32B(14)#define PPC405_UIC0_CR_EIC		_ONEBIT32B(15)#define PPC405_UIC0_CR_EPSIC	_ONEBIT32B(16)#define PPC405_UIC0_CR_ECIC		_ONEBIT32B(17)#define PPC405_UIC0_CR_PPMIC	_ONEBIT32B(18)#define PPC405_UIC0_CR_EIR0C	_ONEBIT32B(25)#define PPC405_UIC0_CR_EIR1C	_ONEBIT32B(26)#define PPC405_UIC0_CR_EIR2C	_ONEBIT32B(27)#define PPC405_UIC0_CR_EIR3C	_ONEBIT32B(28)#define PPC405_UIC0_CR_EIR4C	_ONEBIT32B(29)#define PPC405_UIC0_CR_EIR5C	_ONEBIT32B(30)#define PPC405_UIC0_CR_EIR6C	_ONEBIT32B(31)/* * UIC Enable Register */#define PPC405_UIC0_ER_U0IE		_ONEBIT32B(0)#define PPC405_UIC0_ER_U1IE		_ONEBIT32B(1)#define PPC405_UIC0_ER_IICIE	_ONEBIT32B(2)#define PPC405_UIC0_ER_EMIE		_ONEBIT32B(3)#define PPC405_UIC0_ER_PCIIE	_ONEBIT32B(4)#define PPC405_UIC0_ER_D0IE		_ONEBIT32B(5)#define PPC405_UIC0_ER_D1IE		_ONEBIT32B(6)#define PPC405_UIC0_ER_D2IE		_ONEBIT32B(7)#define PPC405_UIC0_ER_D3IE		_ONEBIT32B(8)#define PPC405_UIC0_ER_EWIE		_ONEBIT32B(9)#define PPC405_UIC0_ER_MSIE		_ONEBIT32B(10)#define PPC405_UIC0_ER_MTEIE	_ONEBIT32B(11)#define PPC405_UIC0_ER_MREIE	_ONEBIT32B(12)#define PPC405_UIC0_ER_MTDIE	_ONEBIT32B(13)#define PPC405_UIC0_ER_MRDIE	_ONEBIT32B(14)#define PPC405_UIC0_ER_EIE		_ONEBIT32B(15)#define PPC405_UIC0_ER_EPSIE	_ONEBIT32B(16)#define PPC405_UIC0_ER_ECIE		_ONEBIT32B(17)#define PPC405_UIC0_ER_PPMIE	_ONEBIT32B(18)#define PPC405_UIC0_ER_EIR0E	_ONEBIT32B(25)#define PPC405_UIC0_ER_EIR1E	_ONEBIT32B(26)
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