📄 405cpu.h

📁 qnx powerpc MPC8245的 BSP源文件
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/* * $QNXLicenseC:  * Copyright 2007, QNX Software Systems.   *   * Licensed under the Apache License, Version 2.0 (the "License"). You   * may not reproduce, modify or distribute this software except in   * compliance with the License. You may obtain a copy of the License   * at: http://www.apache.org/licenses/LICENSE-2.0   *   * Unless required by applicable law or agreed to in writing, software   * distributed under the License is distributed on an "AS IS" basis,   * WITHOUT WARRANTIES OF ANY KIND, either express or implied.  *  * This file may contain contributions from others, either as   * contributors under the License or as licensors under other terms.    * Please review this entire file for other proprietary rights or license   * notices, as well as the QNX Development Suite License Guide at   * http://licensing.qnx.com/license-guide/ for other information.  * $  *//* *  ppc/405cpu.h * * Registers specific to the 405 chip * */#ifndef __PPC_405CPU_H_INCLUDED#define __PPC_405CPU_H_INCLUDED#ifndef __PLATFORM_H_INCLUDED#include <sys/platform.h>#endif#ifndef __PPC_400CPU_H_INCLUDED#include _NTO_HDR_(ppc/400cpu.h)#endif#ifndef __PPC_IBMUIC_H_INCLUDED#include _NTO_HDR_(ppc/ibmuic.h)#endif/* * Bus Error Syndrome Register 0 Bits */#define PPC405_BESR0_M0ET_MASK		_BITFIELD32B(2, 7)#define PPC405_BESR0_M0ET_NOERR		_BITFIELD32B(2, 0)#define PPC405_BESR0_M0ET_RSVD1		_BITFIELD32B(2, 1)#define PPC405_BESR0_M0ET_ECCUE1	_BITFIELD32B(2, 2)#define PPC405_BESR0_M0ET_ECCUE2	_BITFIELD32B(2, 3)#define PPC405_BESR0_M0ET_RSVD2		_BITFIELD32B(2, 4)#define PPC405_BESR0_M0ET_RSVD3		_BITFIELD32B(2, 5)#define PPC405_BESR0_M0ET_RSVD4		_BITFIELD32B(2, 6)#define PPC405_BESR0_M0ET_RSVD5		_BITFIELD32B(2, 7)#define PPC405_BESR0_M0RWS			_ONEBIT32B(3)#define PPC405_BESR0_M0FL			_ONEBIT32B(4)#define PPC405_BESR0_M0AL			_ONEBIT32B(5)#define PPC405_BESR0_M1ET_MASK		_BITFIELD32B(8, 7)#define PPC405_BESR0_M1ET_NOERR		_BITFIELD32B(8, 0)#define PPC405_BESR0_M1ET_RSVD1		_BITFIELD32B(8, 1)#define PPC405_BESR0_M1ET_ECCUE1	_BITFIELD32B(8, 2)#define PPC405_BESR0_M1ET_ECCUE2	_BITFIELD32B(8, 3)#define PPC405_BESR0_M1ET_RSVD2		_BITFIELD32B(8, 4)#define PPC405_BESR0_M1ET_RSVD3		_BITFIELD32B(8, 5)#define PPC405_BESR0_M1ET_RSVD4		_BITFIELD32B(8, 6)#define PPC405_BESR0_M1ET_RSVD5		_BITFIELD32B(8, 7)#define PPC405_BESR0_M1RWS			_ONEBIT32B(9)#define PPC405_BESR0_M1FL			_ONEBIT32B(10)#define PPC405_BESR0_M1AL			_ONEBIT32B(11)#define PPC405_BESR0_M2ET_MASK		_BITFIELD32B(14, 7)#define PPC405_BESR0_M2ET_NOERR		_BITFIELD32B(14, 0)#define PPC405_BESR0_M2ET_RSVD1		_BITFIELD32B(14, 1)#define PPC405_BESR0_M2ET_ECCUE1	_BITFIELD32B(14, 2)#define PPC405_BESR0_M2ET_ECCUE2	_BITFIELD32B(14, 3)#define PPC405_BESR0_M2ET_RSVD2		_BITFIELD32B(14, 4)#define PPC405_BESR0_M2ET_RSVD3		_BITFIELD32B(14, 5)#define PPC405_BESR0_M2ET_RSVD4		_BITFIELD32B(14, 6)#define PPC405_BESR0_M2ET_RSVD5		_BITFIELD32B(14, 7)#define PPC405_BESR0_M2RWS			_ONEBIT32B(15)#define PPC405_BESR0_M2FL			_ONEBIT32B(16)#define PPC405_BESR0_M2AL			_ONEBIT32B(17)#define PPC405_BESR0_M3ET_MASK		_BITFIELD32B(20, 7)#define PPC405_BESR0_M3ET_NOERR		_BITFIELD32B(20, 0)#define PPC405_BESR0_M3ET_RSVD1		_BITFIELD32B(20, 1)#define PPC405_BESR0_M3ET_ECCUE1	_BITFIELD32B(20, 2)#define PPC405_BESR0_M3ET_ECCUE2	_BITFIELD32B(20, 3)#define PPC405_BESR0_M3ET_RSVD2		_BITFIELD32B(20, 4)#define PPC405_BESR0_M3ET_RSVD3		_BITFIELD32B(20, 5)#define PPC405_BESR0_M3ET_RSVD4		_BITFIELD32B(20, 6)#define PPC405_BESR0_M3ET_RSVD5		_BITFIELD32B(20, 7)#define PPC405_BESR0_M3RWS			_ONEBIT32B(21)#define PPC405_BESR0_M3FL			_ONEBIT32B(22)#define PPC405_BESR0_M3AL			_ONEBIT32B(23)/* * Bus Error Syndrome Register 1 Bits */#define PPC405_BESR0_M4ET_MASK		_BITFIELD32B(2, 7)#define PPC405_BESR0_M4ET_NOERR		_BITFIELD32B(2, 0)#define PPC405_BESR0_M4ET_RSVD1		_BITFIELD32B(2, 1)#define PPC405_BESR0_M4ET_ECCUE1	_BITFIELD32B(2, 2)#define PPC405_BESR0_M4ET_ECCUE2	_BITFIELD32B(2, 3)#define PPC405_BESR0_M4ET_RSVD2		_BITFIELD32B(2, 4)#define PPC405_BESR0_M4ET_RSVD3		_BITFIELD32B(2, 5)#define PPC405_BESR0_M4ET_RSVD4		_BITFIELD32B(2, 6)#define PPC405_BESR0_M4ET_RSVD5		_BITFIELD32B(2, 7)#define PPC405_BESR0_M4RWS			_ONEBIT32B(3)#define PPC405_BESR0_M4FL			_ONEBIT32B(4)#define PPC405_BESR0_M4AL			_ONEBIT32B(5)#define PPC405_BESR0_M5ET_MASK		_BITFIELD32B(8, 7)#define PPC405_BESR0_M5ET_NOERR		_BITFIELD32B(8, 0)#define PPC405_BESR0_M5ET_RSVD1		_BITFIELD32B(8, 1)#define PPC405_BESR0_M5ET_ECCUE1	_BITFIELD32B(8, 2)#define PPC405_BESR0_M5ET_ECCUE2	_BITFIELD32B(8, 3)#define PPC405_BESR0_M5ET_RSVD2		_BITFIELD32B(8, 4)#define PPC405_BESR0_M5ET_RSVD3		_BITFIELD32B(8, 5)#define PPC405_BESR0_M5ET_RSVD4		_BITFIELD32B(8, 6)#define PPC405_BESR0_M5ET_RSVD5		_BITFIELD32B(8, 7)#define PPC405_BESR0_M5RWS			_ONEBIT32B(9)#define PPC405_BESR0_M5FL			_ONEBIT32B(10)#define PPC405_BESR0_M5AL			_ONEBIT32B(11)#define PPC405_BESR0_M6ET_MASK		_BITFIELD32B(14, 7)#define PPC405_BESR0_M6ET_NOERR		_BITFIELD32B(14, 0)#define PPC405_BESR0_M6ET_RSVD1		_BITFIELD32B(14, 1)#define PPC405_BESR0_M6ET_ECCUE1	_BITFIELD32B(14, 2)#define PPC405_BESR0_M6ET_ECCUE2	_BITFIELD32B(14, 3)#define PPC405_BESR0_M6ET_RSVD2		_BITFIELD32B(14, 4)#define PPC405_BESR0_M6ET_RSVD3		_BITFIELD32B(14, 5)#define PPC405_BESR0_M6ET_RSVD4		_BITFIELD32B(14, 6)#define PPC405_BESR0_M6ET_RSVD5		_BITFIELD32B(14, 7)#define PPC405_BESR0_M6RWS			_ONEBIT32B(15)#define PPC405_BESR0_M6FL			_ONEBIT32B(16)#define PPC405_BESR0_M6AL			_ONEBIT32B(17)#define PPC405_BESR0_M7ET_MASK		_BITFIELD32B(20, 7)#define PPC405_BESR0_M7ET_NOERR		_BITFIELD32B(20, 0)#define PPC405_BESR0_M7ET_RSVD1		_BITFIELD32B(20, 1)#define PPC405_BESR0_M7ET_ECCUE1	_BITFIELD32B(20, 2)#define PPC405_BESR0_M7ET_ECCUE2	_BITFIELD32B(20, 3)#define PPC405_BESR0_M7ET_RSVD2		_BITFIELD32B(20, 4)#define PPC405_BESR0_M7ET_RSVD3		_BITFIELD32B(20, 5)#define PPC405_BESR0_M7ET_RSVD4		_BITFIELD32B(20, 6)#define PPC405_BESR0_M7ET_RSVD5		_BITFIELD32B(20, 7)#define PPC405_BESR0_M7RWS			_ONEBIT32B(21)#define PPC405_BESR0_M7FL			_ONEBIT32B(22)#define PPC405_BESR0_M7AL			_ONEBIT32B(23) /* * Core Configuration Register 0 */#define PPC405_CCR0_LWL				_ONEBIT32B(6)#define PPC405_CCR0_LWOA			_ONEBIT32B(7)#define PPC405_CCR0_SWOA			_ONEBIT32B(8)#define PPC405_CCR0_DPP1			_ONEBIT32B(9)#define PPC405_CCR0_IPP_MASK		_BITFIELD32B(11,3)#define PPC405_CCR0_IPP_LOWEST		_BITFIELD32B(11,0)#define PPC405_CCR0_IPP_NEXTLOWEST	_BITFIELD32B(11,1)#define PPC405_CCR0_IPP_NEXTHIGHEST	_BITFIELD32B(11,2)#define PPC405_CCR0_IPP_HIGHEST		_BITFIELD32B(11,3)#define PPC405_CCR0_DU0				_ONEBIT32B(14)#define PPC405_CCR0_LDBE			_ONEBIT32B(15)#define PPC405_CCR0_PFC				_ONEBIT32B(20)#define PPC405_CCR0_PFNC			_ONEBIT32B(21)#define PPC405_CCR0_NCRS			_ONEBIT32B(22)#define PPC405_CCR0_FWOA			_ONEBIT32B(23)#define PPC405_CCR0_CIS				_ONEBIT32B(27)#define PPC405_CCR0_CWS				_ONEBIT32B(31)/* * Chip Control Register 0 */#define PPC405_CPC0_CR0_PRE				_ONEBIT32B(0)#define PPC405_CPC0_CR0_GPIO_10_EN		_ONEBIT32B(5)#define PPC405_CPC0_CR0_GPIO_11_EN		_ONEBIT32B(6)#define PPC405_CPC0_CR0_GPIO_12_EN		_ONEBIT32B(7)#define PPC405_CPC0_CR0_GPIO_13_EN		_ONEBIT32B(8)#define PPC405_CPC0_CR0_GPIO_14_EN		_ONEBIT32B(9)#define PPC405_CPC0_CR0_GPIO_15_EN		_ONEBIT32B(10)#define PPC405_CPC0_CR0_GPIO_16_EN		_ONEBIT32B(11)#define PPC405_CPC0_CR0_GPIO_17_EN		_ONEBIT32B(12)#define PPC405_CPC0_CR0_GPIO_18_EN		_ONEBIT32B(13)#define PPC405_CPC0_CR0_GPIO_19_EN		_ONEBIT32B(14)#define PPC405_CPC0_CR0_GPIO_20_EN		_ONEBIT32B(15)#define PPC405_CPC0_CR0_GPIO_21_EN		_ONEBIT32B(16)#define PPC405_CPC0_CR0_GPIO_22_EN		_ONEBIT32B(17)#define PPC405_CPC0_CR0_GPIO_23_EN		_ONEBIT32B(18)#define PPC405_CPC0_CR0_DCS				_ONEBIT32B(19)#define PPC405_CPC0_CR0_RCS				_ONEBIT32B(20)#define PPC405_CPC0_CR0_DTE				_ONEBIT32B(21)#define PPC405_CPC0_CR0_DRE				_ONEBIT32B(22)#define PPC405_CPC0_CR0_DAEC			_ONEBIT32B(23)#define PPC405_CPC0_CR0_U0EC			_ONEBIT32B(24)#define PPC405_CPC0_CR0_U1EC			_ONEBIT32B(25)#define PPC405_CPC0_CR0_UDIV_MASK		_BITFIELD32B(30, 0x1f)#define PPC405_CPC0_CR0_UDIV_SHIFT		(31-30)/* * Chip Pin-Strapping Register */#define PPC405_CPC0_PSR_PFWD_MASK	_BITFIELD32B(1, 3)#define PPC405_CPC0_PSR_PFWD_BYPASS	_BITFIELD32B(1, 0)#define PPC405_CPC0_PSR_PFWD_DIV3	_BITFIELD32B(1, 1)#define PPC405_CPC0_PSR_PFWD_DIV4	_BITFIELD32B(1, 2)#define PPC405_CPC0_PSR_PFWD_DIV6	_BITFIELD32B(1, 3)#define PPC405_CPC0_PSR_PFBD_MASK	_BITFIELD32B(3, 3)#define PPC405_CPC0_PSR_PFBD_DIV1	_BITFIELD32B(3, 0)#define PPC405_CPC0_PSR_PFBD_DIV2	_BITFIELD32B(3, 1)#define PPC405_CPC0_PSR_PFBD_DIV3	_BITFIELD32B(3, 2)#define PPC405_CPC0_PSR_PFBD_DIV4	_BITFIELD32B(3, 3)#define PPC405_CPC0_PSR_PT_MASK		_BITFIELD32B(6, 7)#define PPC405_CPC0_PSR_PT_CHOICE1	_BITFIELD32B(6, 0)#define PPC405_CPC0_PSR_PT_CHOICE2	_BITFIELD32B(6, 1)#define PPC405_CPC0_PSR_PT_CHOICE3	_BITFIELD32B(6, 2)#define PPC405_CPC0_PSR_PT_CHOICE4	_BITFIELD32B(6, 3)#define PPC405_CPC0_PSR_PT_CHOICE5	_BITFIELD32B(6, 4)#define PPC405_CPC0_PSR_PT_CHOICE6	_BITFIELD32B(6, 5)#define PPC405_CPC0_PSR_PT_CHOICE7	_BITFIELD32B(6, 6)#define PPC405_CPC0_PSR_PT_CHOICE8	_BITFIELD32B(6, 7)#define PPC405_CPC0_PSR_PDC_MASK	_BITFIELD32B(8, 3)#define PPC405_CPC0_PSR_PDC_DIV1	_BITFIELD32B(8, 0)#define PPC405_CPC0_PSR_PDC_DIV2	_BITFIELD32B(8, 1)#define PPC405_CPC0_PSR_PDC_DIV3	_BITFIELD32B(8, 2)#define PPC405_CPC0_PSR_PDC_DIV4	_BITFIELD32B(8, 3)#define PPC405_CPC0_PSR_ODP_MASK	_BITFIELD32B(10, 3)#define PPC405_CPC0_PSR_ODP_DIV1	_BITFIELD32B(10, 0)#define PPC405_CPC0_PSR_ODP_DIV2	_BITFIELD32B(10, 1)#define PPC405_CPC0_PSR_ODP_DIV3	_BITFIELD32B(10, 2)#define PPC405_CPC0_PSR_ODP_DIV4	_BITFIELD32B(10, 3)#define PPC405_CPC0_PSR_PDP_MASK	_BITFIELD32B(12, 3)#define PPC405_CPC0_PSR_PDP_DIV1	_BITFIELD32B(12, 0)#define PPC405_CPC0_PSR_PDP_DIV2	_BITFIELD32B(12, 1)#define PPC405_CPC0_PSR_PDP_DIV3	_BITFIELD32B(12, 2)#define PPC405_CPC0_PSR_PDP_DIV4	_BITFIELD32B(12, 3)#define PPC405_CPC0_PSR_EBDP_MASK	_BITFIELD32B(12, 3)#define PPC405_CPC0_PSR_EBDP_DIV2	_BITFIELD32B(14, 0)#define PPC405_CPC0_PSR_EBDP_DIV3	_BITFIELD32B(14, 1)#define PPC405_CPC0_PSR_EBDP_DIV4	_BITFIELD32B(14, 2)#define PPC405_CPC0_PSR_EBDP_DIV5	_BITFIELD32B(14, 3)#define PPC405_CPC0_PSR_RW_MASK		_BITFIELD32B(16, 3)#define PPC405_CPC0_PSR_RW_8		_BITFIELD32B(16, 0)#define PPC405_CPC0_PSR_RW_16		_BITFIELD32B(16, 1)#define PPC405_CPC0_PSR_RW_32		_BITFIELD32B(16, 2)#define PPC405_CPC0_PSR_RW_RSVD		_BITFIELD32B(16, 3)#define PPC405_CPC0_PSR_RL			_ONEBIT32B(17)#define PPC405_CPC0_PSR_PAME		_ONEBIT32B(19)#define PPC405_CPC0_PSR_PAE			_ONEBIT32B(21)/* * CPM Enable RegisterNYI: *//* * CPM Force RegisterNYI: *//* * CPM Status RegisterNYI: *//* * Debug Control Register 0 */#define PPC405_DBCR0_EDM			_ONEBIT32B(0)#define PPC405_DBCR0_IDM			_ONEBIT32B(1)#define PPC405_DBCR0_RST_MASK		_BITFIELD32B(3, 3)#define PPC405_DBCR0_RST_NORESET	_BITFIELD32B(3, 0)#define PPC405_DBCR0_RST_CORE		_BITFIELD32B(3, 1)#define PPC405_DBCR0_RST_CHIP		_BITFIELD32B(3, 2)#define PPC405_DBCR0_RST_SYSTEM		_BITFIELD32B(3, 3)#define PPC405_DBCR0_IC				_ONEBIT32B(4)#define PPC405_DBCR0_BT				_ONEBIT32B(5)#define PPC405_DBCR0_EDE			_ONEBIT32B(6)#define PPC405_DBCR0_TDE			_ONEBIT32B(7)#define PPC405_DBCR0_IA1			_ONEBIT32B(8)#define PPC405_DBCR0_IA2			_ONEBIT32B(9)#define PPC405_DBCR0_IA12			_ONEBIT32B(10)#define PPC405_DBCR0_IA12X			_ONEBIT32B(11)#define PPC405_DBCR0_IA3			_ONEBIT32B(12)#define PPC405_DBCR0_IA4			_ONEBIT32B(13)#define PPC405_DBCR0_IA34			_ONEBIT32B(14)#define PPC405_DBCR0_IA34X			_ONEBIT32B(15)#define PPC405_DBCR0_IA12T			_ONEBIT32B(16)#define PPC405_DBCR0_IA34T			_ONEBIT32B(17)#define PPC405_DBCR0_FT				_ONEBIT32B(31)/* * Debug Control Register 1 */#define PPC405_DBCR1_D1R			_ONEBIT32B(0)#define PPC405_DBCR1_D2R			_ONEBIT32B(1)#define PPC405_DBCR1_D1W			_ONEBIT32B(2)#define PPC405_DBCR1_D2W			_ONEBIT32B(3)#define PPC405_DBCR1_D1S_MASK		_BITFIELD32B(5, 3)#define PPC405_DBCR1_D1S_ALL		_BITFIELD32B(5, 0)#define PPC405_DBCR1_D1S_IGN1LSB	_BITFIELD32B(5, 1)#define PPC405_DBCR1_D1S_IGN2LSB	_BITFIELD32B(5, 2)#define PPC405_DBCR1_D1S_IGN5LSB	_BITFIELD32B(5, 3)#define PPC405_DBCR1_D2S_MASK		_BITFIELD32B(7, 3)#define PPC405_DBCR1_D2S_ALL		_BITFIELD32B(7, 0)#define PPC405_DBCR1_D2S_IGN1LSB	_BITFIELD32B(7, 1)#define PPC405_DBCR1_D2S_IGN2LSB	_BITFIELD32B(7, 2)#define PPC405_DBCR1_D2S_IGN5LSB	_BITFIELD32B(7, 3)#define PPC405_DBCR1_DA12			_ONEBIT32B(8)#define PPC405_DBCR1_DA12X			_ONEBIT32B(9)#define PPC405_DBCR1_DV1M_MASK		_BITFIELD32B(13, 3)#define PPC405_DBCR1_DV1M_UNDEF		_BITFIELD32B(13, 0)#define PPC405_DBCR1_DV1M_AND		_BITFIELD32B(13, 1)#define PPC405_DBCR1_DV1M_OR		_BITFIELD32B(13, 2)#define PPC405_DBCR1_DV1M_ANDOR		_BITFIELD32B(13, 3)#define PPC405_DBCR1_DV2M_MASK		_BITFIELD32B(15, 3)#define PPC405_DBCR1_DV2M_UNDEF		_BITFIELD32B(15, 0)#define PPC405_DBCR1_DV2M_AND		_BITFIELD32B(15, 1)#define PPC405_DBCR1_DV2M_OR		_BITFIELD32B(15, 2)#define PPC405_DBCR1_DV2M_ANDOR		_BITFIELD32B(15, 3)#define PPC405_DBCR1_DV1BE_MASK		_BITFIELD32B(19, 0xf)#define PPC405_DBCR1_DV1BE_SHIFT	(31-19)#define PPC405_DBCR1_DV2BE_MASK		_BITFIELD32B(23, 0xf)#define PPC405_DBCR1_DV2BE_SHIFT	(31-23)/* * DMA Channel Control Registers 0-3NYI: *//* * DMA Polarity Configuration RegisterNYI: *//* * DMA Scatter/Gather Command RegisterNYI: *//* * DMA Sleep Mode RegisterNYI: *//* * DMA Status RegisterNYI: *//* * ECC Configuration RegisterNYI: *//* * ECC Error Status RegisterNYI: *//* * (Ethernet) Interrupt Status Enable RegisterNYI: *//* * (Ethernet) Interrupt Status RegisterNYI: *//* * (Ethernet) Mode Register 0NYI: *//* * (Ethernet) Mode Register 1NYI: *//* * (Ethernet) Receive Mode RegisterNYI: *//* * (Ethernet) Receive Low/High Water Mark RegisterNYI:
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