mpc85xx.h

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */




#ifndef	_MPC85XX_INCLUDED
#define	_MPC85XX_INCLUDED

#include <atomic.h>
#include <ctype.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <stddef.h>
#include <stdlib.h>
#include <string.h>
#include <pthread.h>
#include <syslog.h>
#include <net/if.h>
#include <net/if_dl.h>
#include <net/if_types.h>
#include <sys/mman.h>
#include <sys/mbuf.h>
#include <sys/types.h>
#include <sys/siginfo.h>
#include <sys/neutrino.h>
#include <sys/io-net.h>
#include <sys/dcmd_io-net.h>
#include <sys/slogcodes.h>
#include <sys/cache.h>
#include <sys/syspage.h>
#include <hw/inout.h>
#include <hw/sysinfo.h>
#include <ppc/85xxintr.h>
#include <ppc/83xxintr.h>

#include <drvr/mdi.h>
#include <drvr/eth.h>
#include <drvr/nicsupport.h>

#include <hw/pci.h>
#include <hw/pci_devices.h>


#define	MPC_TSEC1_BASE		0x24000
#define	MPC_TSEC2_BASE		0x25000
#define	MPC_TSEC3_BASE		0x26000
#define	MPC_TSEC4_BASE		0x27000

#define NIC_INTR_EVENT_TX	0
#define NIC_INTR_EVENT_RX	1
#define NIC_INTR_EVENT_ERR	3

#define MPC_KEEP_PACKET		0x100000
#define MPC_DEFRAG_PACKET	0x1000000

#define MPC_MTU_SIZE		1536
#define MAX_DN_FRAGMENTS	8

#define DEFAULT_NUM_RX_DESCRIPTORS  64
#define DEFAULT_NUM_TX_DESCRIPTORS  256

#define MIN_NUM_RX_DESCRIPTORS  16
#define MIN_NUM_TX_DESCRIPTORS  16
#define MAX_NUM_RX_DESCRIPTORS  2048
#define MAX_NUM_TX_DESCRIPTORS  2048

#define MPC_DEFAULT_MAX_PACKETS 200

#define	MPC_TIMEOUT		1000

/* TSEC General Control and Status Registers */

#define	MPC_IEVENT			(0x0010 >> 2)	/* Interrupt event register */
	#define	IEVENT_BABR		(1 << 31)		/* Babbling receive error */
	#define	IEVENT_RXC		(1 << 30)		/* Receive control interrupt */
	#define	IEVENT_BSY		(1 << 29)		/* Busy condition interrupt */
	#define	IEVENT_EBERR	(1 << 28)		/* Ethernet bus error */
	#define	IEVENT_MSRO		(1 << 26)		/* MSTAT register overflow */
	#define	IEVENT_GTSC		(1 << 25)		/* Graceful transmit stop complete */
	#define	IEVENT_BABT		(1 << 24)		/* Babbling transmit error */
	#define	IEVENT_TXC		(1 << 23)		/* Transmit control interrupt */
	#define	IEVENT_TXE		(1 << 22)		/* Transmit error */
	#define	IEVENT_TXB		(1 << 21)		/* Transmit buffer */
	#define	IEVENT_TXF		(1 << 20)		/* Transmit frame interrupt */
	#define	IEVENT_LC		(1 << 18)		/* Late collision */
	#define	IEVENT_CRL		(1 << 17)		/* Collision retry limit */
	#define	IEVENT_XFUN		(1 << 16)		/* Transmit FIFO underrun */
	#define	IEVENT_RXBO		(1 << 15)		/* Receive buffer */
	#define	IEVENT_GRSC		(1 << 8)		/* Graceful receive stop complete */
	#define	IEVENT_RXFO		(1 << 7)		/* Receive frame interrupt */

#define	MPC_IMASK			(0x0014 >> 2)	/* Interrupt mask register */
	#define	IMASK_BABR		(1 << 31)		/* Babbling receive error */
	#define	IMASK_RXC		(1 << 30)		/* Receive control interrupt */
	#define	IMASK_BSY		(1 << 29)		/* Busy condition interrupt */
	#define	IMASK_EBERR		(1 << 28)		/* Ethernet bus error */
	#define	IMASK_MSRO		(1 << 26)		/* MSTAT register overflow */
	#define	IMASK_GTSC		(1 << 25)		/* Grace transmit stop complete */
	#define	IMASK_BABT		(1 << 24)		/* Babbling transmit error */
	#define	IMASK_TXC		(1 << 23)		/* Transmit control interrupt */
	#define	IMASK_TXE		(1 << 22)		/* Transmit error */
	#define	IMASK_TXB		(1 << 21)		/* Transmit buffer */
	#define	IMASK_TXF		(1 << 20)		/* Transmit frame interrupt */
	#define	IMASK_LC		(1 << 18)		/* Late collision */
	#define	IMASK_CRL		(1 << 17)		/* Collision retry limit */
	#define	IMASK_XFUN		(1 << 16)		/* Transmit FIFO underrun */
	#define	IMASK_RXBO		(1 << 15)		/* Receive buffer */
	#define	IMASK_GRSC		(1 << 8)		/* Graceful receive stop complete */
	#define	IMASK_RXFO		(1 << 7)		/* Receive frame interrupt */

#define	MPC_EDIS			(0x0018 >> 2)	/* Error disable register */
	#define	EDIS_BSYDIS		(1 << 29)		/* Busy disable */
	#define	EDIS_EBERRDIS	(1 << 28)		/* Ethernet controller bus error disable */
	#define	EDIS_TXEDIS		(1 << 22)		/* Transmit error disable */
	#define	EDIS_LCDIS		(1 << 18)		/* Late collision disable */
	#define	EDIS_CRLDIS		(1 << 17)		/* Collision retry limit disable */
	#define	EDIS_XFUNDIS	(1 << 16)		/* Transmit fifo underrun disable */

#define	MPC_ECNTRL			(0x0020 >> 2)	/* Ethernet Control register */
	#define	ECNTRL_CLRCNT	(1 << 14)		/* Clear all statistics counters */
	#define	ECNTRL_AUTOZ	(1 << 13)		/* Automatically zero statistics counters */
	#define	ECNTRL_STEN		(1 << 12)		/* Stastics enabled */
	#define	ECNTRL_TBIM		(1 << 5)		/* Ten-bit interface mode */
	#define	ECNTRL_RPM		(1 << 4)		/* Reduced pin mode */
	#define	ECNTRL_R100M	(1 << 3)		/* RGMII 100 mode */
	#define ECNTRL_RMM		(1 << 2)		/* Reduced pin mode for 10/100 */
	
#define	MPC_MINFLR			(0x0024 >> 2)	/* Minimum frame length register */

#define	MPC_PTV				(0x0028 >> 2)	/* Pause time value register */

#define	MPC_DMACTRL			(0x002c >> 2)	/* DMA control register */
	#define	DMACTRL_TDSEN	(1 << 7)		/* Tx Data snoop enable */
	#define	DMACTRL_TBDSEN	(1 << 6)		/* TxBD snoop enable */
	#define	DMACTRL_GRS		(1 << 4)		/* Graceful receive stop */
	#define	DMACTRL_GTS		(1 << 3)		/* Graceful transmit stop */
	#define	DMACTRL_TOD		(1 << 2)		/* Transmit on demand */
	#define	DMACTRL_WWR		(1 << 1)		/* Write with response */
	#define	DMACTRL_WOP		(1 << 0)		/* Wait or poll */

#define	MPC_TBIPA			(0x0030 >> 2)	/* TBI PHY address register */

/* TSEC FIFO Control and Status Registers */

#define	MPC_FIFO_TX_THR		(0x008c >> 2)	/* FIFO transmit threshold register */
#define	MPC_FIFO_TX_STARVE	(0x0098 >> 2)	/* FIFO transmit starve register */
#define	MPC_FIFO_TX_STARVE_SHUTOFF	(0x009c >> 2)	/* FIFO transmit starve shutoff register */

/* TSEC Transmit Control and Status Registers */

#define	MPC_TCTRL			(0x0100 >> 2)	/* Transmit control register */
	#define	TCTRL_THDF		(1 << 11)		/* Transmit half-duplex flow control */
	#define	TCTRL_RFC_PAUSE	(1 << 4)		/* Receive flow control pause frame */
	#define	TCTRL_TFC_PAUSE	(1 << 3)		/* Transmit flow control pause frame */

#define	MPC_TSTAT			(0x0104 >> 2)	/* Transmit status register */
	#define	TSTAT_THLT		(1 << 31)		/* Transmit halt */

#define MPC_TBDLEN			(0x010c >> 2)	/* TxBD data length */

#define MPC_CTBPTR			(0x0124 >> 2)	/* Current TxBD pointer */

#define MPC_TBPTR			(0x0184 >> 2)	/* TxBD pointer */

#define MPC_TBASE			(0x0204 >> 2)	/* TxBD base address */

#define MPC_OSTBD			(0x02b0 >> 2)	/* Out-of-sequence TxBD register */
	#define	OSTBD_R			(1 << 31)		/* Ready */
	#define	OSTBD_PAD		(1 << 30)		/* Padding for short frames */
	#define	OSTBD_W			(1 << 29)		/* Wrap */
	#define	OSTBD_I			(1 << 28)		/* Interrupt */
	#define	OSTBD_L			(1 << 27)		/* Last in frame */
	#define	OSTBD_TC		(1 << 26)		/* Tx CRC */
	#define	OSTBD_DEF		(1 << 25)		/* Defer indication */
	#define	OSTBD_LC		(1 << 23)		/* Late collision */
	#define	OSTBD_RL		(1 << 22)		/* Retransmission limit */
	#define	OSTBD_RC(x)		((x & 0x0f) << 18)	/* Retry count */
	#define	OSTBD_UN		(1 << 17)		/* Underrun */

#define MPC_OSTBDP			(0x02b4 >> 2)	/* Out-of-sequence Tx data buffer pointer register */

/* TSEC Receive Control and Status Registers */

#define MPC_RCTRL			(0x0300 >> 2)	/* Receive control register */
	#define	RCTRL_BC_REJ	(1 << 4)		/* Broadcast frame reject */
	#define	RCTRL_PROM		(1 << 3)		/* Promiscuous mode */
	#define	RCTRL_RSF		(1 << 2)		/* Receive short frame mode */

#define MPC_RSTAT			(0x0304 >> 2)	/* Receive status register */
	#define	RSTAT_QHLT		(1 << 23)		/* RxBD queue is halted */

#define MPC_RBDLEN			(0x030c >> 2)	/* RxBD data length */
#define MPC_CRBPTR			(0x0324 >> 2)	/* Current RxBD pointer */
#define MPC_MRBLR			(0x0340 >> 2)	/* Maximum receive buffer length register */
#define MPC_RBPTR			(0x0384 >> 2)	/* RxBD pointer */
#define MPC_RBASE			(0x0404 >> 2)	/* RxBD base address */

/* TSEC MAC Registers */

#define MPC_MACCFG1			(0x0500 >> 2)	/* MAC Configuration #1 */
	#define	MACCFG1_SFT_RESET	(1 << 31)	/* Soft reset */
	#define	MACCFG1_RST_RXMC	(1 << 19)	/* Reset receive MAC control block */
	#define	MACCFG1_RST_TXMC	(1 << 18)	/* Reset transmit MAC control block */
	#define	MACCFG1_RST_RXFUN	(1 << 17)	/* Reset receive function block */
	#define	MACCFG1_RST_TXFUN	(1 << 16)	/* Reset transmit function block */
	#define	MACCFG1_LP_BACK		(1 << 8)	/* Loop back */
	#define	MACCFG1_RX_FLOW		(1 << 5)	/* Receive flow */
	#define	MACCFG1_TX_FLOW		(1 << 4)	/* Transmit flow */
	#define	MACCFG1_SYNC_RXEN	(1 << 3)	/* Receive enable synchronized */
	#define	MACCFG1_RXEN		(1 << 2)	/* Receive enable */
	#define	MACCFG1_SYNC_TXEN	(1 << 1)	/* Transmit enable synchronized */
	#define	MACCFG1_TXEN		(1 << 0)	/* Transmit enable */

#define MPC_MACCFG2			(0x0504 >> 2)	/* MAC Configuration #2 */
	#define	MACCFG2_PRE_LEN(x)	((x & 0x0f) << 12)	/* Preamble length */
	#define	MACCFG2_IF_MODE_NIB	(1 << 8)	/* Nibble mode (MII) */
	#define	MACCFG2_IF_MODE_BYT	(2 << 8)	/* Byte mode (TBI) */
	#define	MACCFG2_IF			(MACCFG2_IF_MODE_NIB | MACCFG2_IF_MODE_BYT)
	#define	MACCFG2_HUGE_FRM	(1 << 5)	/* Huge frame enable */
	#define	MACCFG2_LCHECK		(1 << 4)	/* Length check */
	#define	MACCFG2_PAD_CRC		(1 << 2)	/* Pad and append CRC */
	#define	MACCFG2_CRC_EN		(1 << 1)	/* CRC enable */
	#define	MACCFG2_FDX			(1 << 0)	/* Full duplex configure */

#define	MPC_IPGIFGI			(0x0508 >> 2)	/* Inter packet / frame gap */

#define MPC_HAFDUP			(0x050c >> 2)	/* Half-duplex */

#define MPC_MAXFRM			(0x0510 >> 2)	/* Maximum frame */

#define MPC_MIIMCFG			(0x0520 >> 2)	/* MII Mgmt: configuration */
	#define	MIIMCFG_RESET	(1 << 31)		/* Reset management */
	#define	MIIMCFG_NOPRE	(1 << 4)		/* Preamble suppress */

#define MPC_MIICOM			(0x0524 >> 2)	/* MII Mgmt: command */
	#define	MIICOM_SCAN		(1 << 1)		/* Scan cycle */
	#define	MIICOM_READ		(1 << 0)		/* Read cycle */

#define MPC_MIIMADD			(0x0528 >> 2)	/* MII Mgmt: address */
	#define	MIIMADD_PHYADD(x)	((x & 0x1f) << 8)	/* PHY address */
	#define	MIIMADD_REGADD(x)	(x & 0x1f)	/* Register address */

#define MPC_MIIMCON			(0x052c >> 2)	/* MII Mgmt: control */

#define MPC_MIIMSTAT		(0x0530 >> 2)	/* MII Mgmt: status */