init_intrinfo.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */




#include "startup.h"
#include <ppc/85xxcpu.h>
#include <ppc/85xxintr.h>
#include "pic_85xx.h"

extern short cpm;

#define PIC_IN(r)		in32( base+ (PPC85xx_CCSR_OFF_##r))
#define PIC_OUT(r,v)	out32(base+ (PPC85xx_CCSR_OFF_##r),v)


//
// Initialize interrupt controller hardware & intrinfo structure in the
// system page.
// This code is hardware dependant and may have to be changed
// changed by end users.
//
// This version is for the Motorola PPC 85x0ADS evaluation board

const static struct startup_intrinfo intrs[] = {
	PPC85xx_INTRS()

	{ 	PPC_INTR_DECREMENTER, 1, _NTO_INTR_SPARE,
		PPCBKE_SPR_IVOR10, 0, 0,
		{INTR_GENFLAG_NOGLITCH, 0, &interrupt_id_booke_dec},
		{0, 0, &interrupt_eoi_booke_dec},
		&interrupt_mask_booke_dec, &interrupt_unmask_booke_dec, 0,
		0
	},
	{ 	PPC_INTR_FIT, 1, _NTO_INTR_SPARE,
		PPCBKE_SPR_IVOR11, 0, 0,
		{INTR_GENFLAG_NOGLITCH, 0, &interrupt_id_booke_fit},
		{0, 0, &interrupt_eoi_booke_fit},
		&interrupt_mask_booke_fit, &interrupt_unmask_booke_fit, 0,
		0
	},
	{ 	PPC_INTR_WATCHDOG, 1, _NTO_INTR_SPARE,
		PPCBKE_SPR_IVOR12, 0, PPC_INTR_FLAG_CI,
		{INTR_GENFLAG_NOGLITCH, 0, &interrupt_id_booke_watchdog},
		{0, 0, &interrupt_eoi_booke_watchdog},
		&interrupt_mask_booke_watchdog, &interrupt_unmask_booke_watchdog, 0,
		0
	},
};

const static struct startup_intrinfo intr_cpm[] = {
	PPC85xx_INTRS_CPM()
};

const static struct startup_intrinfo intr_extnd[] = {
	PPC85xx_INTRS_EXTND()
};


void
init_intrinfo() {
	uintptr_t	base;

	base = startup_io_map(MEG(1), immr_paddr);

	add_interrupt_array(intrs, sizeof(intrs));

	ppc85xx_config_pic();

	if (cpm) {
		add_interrupt_array(intr_cpm, sizeof(intr_cpm));
		ppc85xx_config_pic_cpm();
	}
	if (((PIC_IN(FRR) >> PPC85xx_FRR_NIRQ_SHIFT) & 0x7FF) == 0x4F) {
		/* Extended interrupt handling capablities */
		add_interrupt_array(intr_extnd, sizeof(intr_cpm));
	}
	startup_io_unmap(base);

}