hw_sermpsc_mv64360.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */

#include "startup.h"

// Offsets to registers that we use
#define MV64360_BRG0_CFG	0xb200
#define MV64360_BRG1_CFG	0xb208
#define MV64360_MPSC_MRR	0xb400
#define MV64360_MPSC_RCRR	0xb404
#define MV64360_MPSC_TCRR	0xb408
#define MV64360_MPSC0_MMCRL	0x8000
#define MV64360_MPSC0_MMCRH	0x8004
#define MV64360_MPSC0_MPCR	0x8008

#define MV64360_MPSC0_CHR1	0x800c
#define MV64360_MPSC0_CHR2	0x8010
#define MV64360_MPSC0_CHR3	0x8014
#define MV64360_MPSC0_CHR4	0x8018
#define MV64360_MPSC0_CHR5	0x801c
#define MV64360_MPSC0_CHR6	0x8020
#define MV64360_MPSC0_CHR7	0x8024
#define MV64360_MPSC0_CHR8	0x8028
#define MV64360_MPSC0_CHR9	0x802c
#define MV64360_MPSC0_CHR10	0x8030
#define MV64360_MPSC0_CHR11	0x8034


void put_mpsc_mv64360(int c);

static void
parse_line(unsigned channel, const char *line, unsigned *baud, unsigned *clk, unsigned *div) {

    if(*line != '.' && *line != '\0') {
        dbg_device[channel].base = strtopaddr(line, (char **)&line, 16);
        if(*line == '^') dbg_device[channel].shift = strtoul(line+1, (char **)&line, 0);
    }
    if(*line == '.') ++line;
    if(*line != '.' && *line != '\0') *baud = strtoul(line, (char **)&line, 0);
    if(*line == '.') ++line;
    if(*line != '.' && *line != '\0') *clk = strtoul(line, (char **)&line, 0);
    if(*line == '.') ++line;
    if(*line != '.' && *line != '\0') *div = strtoul(line, (char **)&line, 0);

}

void
init_mpsc_mv64360(unsigned channel, const char *init, const char *defaults) {
	unsigned baud;
	unsigned div;
	unsigned clk;
	unsigned cnt;
	paddr_t base;
	unsigned shift;

	if(channel != 0) return;
	// Parse args
	parse_line(channel, defaults, &baud, &clk, &div);
	parse_line(channel, init, &baud, &clk, &div);

	base = dbg_device[channel].base;
	shift = dbg_device[channel].shift;

	chip_access(base, shift, 0, 0xc000);

	// Program MRR MPSC0 and MPSC1 routing to comm pins
	chip_write32(MV64360_MPSC_MRR, ENDIAN_LE32(0x7ffe38));

	// Port Multiplex: RMII, MPSC0 and MPSC1 routing -- done in IPL

	// Pin MPP20 programmed as Bclkin0 in IPL

	// Receive clock routing register -- BRG0
	chip_write32(MV64360_MPSC_RCRR, ENDIAN_LE32(0));

	// Transmit clock routing register -- BRG0
	chip_write32(MV64360_MPSC_TCRR, ENDIAN_LE32(0));

	// set baudrate
	cnt = (clk/div)/(2*baud) - 1; 
	if(cnt == -1) cnt = 0;

	// Program BRG0 -- runs with 3.84mhz clock
	chip_write32(MV64360_BRG0_CFG, ENDIAN_LE32(0x00210000 | 214));
	chip_write32(MV64360_BRG0_CFG, ENDIAN_LE32(0x00210000 | (cnt & 0xffff)));
	chip_write32(0xf00c, ENDIAN_LE32(0x00090000));

	// Setup port registers
	chip_write32(MV64360_MPSC0_MMCRL, ENDIAN_LE32(0x000004c4));
	// Rx/Tx div 16 or 32
	if(div == 32) {
		chip_write32(MV64360_MPSC0_MMCRH, ENDIAN_LE32(0x064007f8));
	} else {
		chip_write32(MV64360_MPSC0_MMCRH, ENDIAN_LE32(0x044005f8));
	}
	
	// Port specific registers
	chip_write32(MV64360_MPSC0_CHR1, ENDIAN_LE32(0x003000ab));
	chip_write32(MV64360_MPSC0_CHR3, ENDIAN_LE32(0x00000000));
	chip_write32(MV64360_MPSC0_CHR4, ENDIAN_LE32(0x00000000));
	chip_write32(MV64360_MPSC0_CHR6, ENDIAN_LE32(0x00000000));
	chip_write32(MV64360_MPSC0_CHR7, ENDIAN_LE32(0x00000000));

	// Enter Hunt
	chip_write32(MV64360_MPSC0_CHR2, ENDIAN_LE32(0x80000000));

	while(chip_read32(MV64360_MPSC0_CHR10) & ENDIAN_LE32(0x20) == 0);

	// 8N1 operation
	chip_write32(MV64360_MPSC0_MPCR, ENDIAN_LE32(0x00003000));

	while(chip_read32(MV64360_MPSC0_CHR10) & ENDIAN_LE32(0x08) == 0);

	chip_done();
}

void
put_mpsc_mv64360(int c) {
	chip_access(dbg_device[0].base, dbg_device[0].shift, 0, 0xc000);
    while(chip_read32(MV64360_MPSC0_CHR2) & ENDIAN_LE32(0x200));
    chip_write32(MV64360_MPSC0_CHR1, ENDIAN_LE32(0x00300000 | (c & 0xff)));
    // Output char
    chip_write32(MV64360_MPSC0_CHR2, ENDIAN_LE32(0x00000200));

	chip_done();

	return;
}