callout_interrupt_raven_mpic.s

qnx powerpc MPC8245的 BSP源文件

#  
# Copyright 2007, QNX Software Systems. 
#  
# Licensed under the Apache License, Version 2.0 (the "License"). You 
# may not reproduce, modify or distribute this software except in 
# compliance with the License. You may obtain a copy of the License 
# at: http://www.apache.org/licenses/LICENSE-2.0 
#  
# Unless required by applicable law or agreed to in writing, software 
# distributed under the License is distributed on an "AS IS" basis, 
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
# 
# This file may contain contributions from others, either as 
# contributors under the License or as licensors under other terms.  
# Please review this entire file for other proprietary rights or license 
# notices, as well as the QNX Development Suite License Guide at 
# http://licensing.qnx.com/license-guide/ for other information.
# 
# An entry point for a hardware kernel callout.
# It may be called by an interrupt handler.
# This code MUST be position independant.
#

	.include "callout.ah"
#
# Interrupts are always off in this code.
#
# Note that interrupt_id_* and interrupt_eoi_* are not actually
# called by the kernel. For performance reasons, they are instead
# copied into place and intermixed with other kernel code. As such,
# they don't follow normal calling conventions. They should just fall out 
# their bottoms when done rather than attempting to do a return 
# instruction. The 'id' routine should return the interrupt level in
# the r14 register. The 'eoi' routine will find it still there. 
# By turning on various INTR_GENFLAG_* bits in the intrinfo_entry,
# the following values can be loaded before entry to this code.
# 
#		cpu number			=> r15
#		syspage_ptr			=> r16
#		intrinfo_entry		=> r17
#		intr mask count		=> r18 (only available in EOI routine)
#
# If the INTR_FLAG_CPU_FAULT bit is on, the eoi routine should set
# the R3 register to the following value to indicate the exception
# that has occurred:
# 		R3 = (fault_number << 16) | (signal_code << 8) | (signal_number)
# Set R3 to zero if no exception has occured. If the exception is memory
# related, set R4 to referenced address that caused the exception, zero
# if there is no address.
#

.set RAVEN_INTACK_0_OFF,	0x200a0
.set RAVEN_INTEOI_0_OFF,	0x200b0
.set RAVEN_INTIPI_OFF,		0x010a0
.set RAVEN_INTTIMER_OFF,	0x01120
.set RAVEN_INTREG_OFF,		0x10000
.set RAVEN_INT_REGOFF_SFT,	5

.set RAVEN_IPI_VEC_FIRST,		0x10
.set RAVEN_IPI_VEC_LAST,		0x13
.set RAVEN_TIMER_VEC_FIRST,		0x14
.set RAVEN_TIMER_VEC_LAST,		0x17

# R3: syspage paddr
# R4: syspage vaddr
# R5: rtn dst offset
# R6: r/w offset
# R7: patch data
# R8: rtn src

patcher:
	stwu	%r1,-32(%r1)
	mflr	%r0
	stw		%r31,28(%r1)
	stw		%r0,36(%r1)
	
	add		%r31,%r3,%r5
	
   	mr		%r4,%r7
	loadi	%r3,0x30000
	bl		callout_io_map_indirect

	lhz		%r4,6(%r31)
	lhz		%r5,2(%r31)
	slwi	%r5,%r5,16
	or		%r4,%r4,%r5
	add		%r3,%r3,%r4
	sth		%r3,6(%r31)
	srwi	%r3,%r3,16
	sth		%r3,2(%r31)
	
	lwz		%r0,36(%r1)
	mtlr	%r0
	lwz		%r31,28(%r1)
	addi	%r1,%r1,32
	blr

.macro DEVBASE reg,dev_reg_off
	# the instruction immediate values are patched by the above routine
	lis		&reg,(&dev_reg_off) >> 16
	ori		&reg,&reg,(&dev_reg_off) & 0xffff
.endm
		

CALLOUT_START	interrupt_id_raven_mpic, 0, patcher
	DEVBASE	%r5,RAVEN_INTACK_0_OFF
	
	rlwinm	%r6,%r15,12,0,31
	lbzx	%r14,%r6,%r5
	eieio

	extsb	%r14,%r14
CALLOUT_END	interrupt_id_raven_mpic


CALLOUT_START	interrupt_eoi_raven_mpic, 0, patcher
	DEVBASE	%r5,RAVEN_INTEOI_0_OFF
	
	rlwinm	%r6,%r15,12,0,31
	li		%r0,0
	stbx	%r0,%r6,%r5
	eieio
CALLOUT_END	interrupt_eoi_raven_mpic


CALLOUT_START	interrupt_unmask_raven_mpic, 0, patcher
	DEVBASE	%r5,RAVEN_INTREG_OFF
	
	cmplwi	%r4,RAVEN_TIMER_VEC_FIRST
	blt		1f
	# handle timers...
	subi	%r4,%r4,RAVEN_TIMER_VEC_FIRST
	loadi	%r6,RAVEN_INTREG_OFF-RAVEN_INTTIMER_OFF
	sub		%r5,%r5,%r6
	b		2f
1:
	cmplwi	%r4,RAVEN_IPI_VEC_FIRST
	blt		2f
	# handle ipis...
	subi	%r4,%r4,RAVEN_IPI_VEC_FIRST
	loadi	%r6,RAVEN_INTREG_OFF-RAVEN_INTIPI_OFF
	sub		%r5,%r5,%r6
	slwi	%r6,%r4,4	# IPI vector registers separated by 0x10
	b		3f
2:
	slwi	%r6,%r4,RAVEN_INT_REGOFF_SFT
3:
	lwzx	%r7,%r5,%r6
	eieio
	rlwinm	%r7,%r7,0,25,23
	stwx	%r7,%r5,%r6
	eieio
	
	li	%r3,0
	blr
CALLOUT_END	interrupt_unmask_raven_mpic


CALLOUT_START	interrupt_mask_raven_mpic, 0, patcher
	DEVBASE	%r5,RAVEN_INTREG_OFF
	
	cmplwi	%r4,RAVEN_TIMER_VEC_FIRST
	blt		1f
	# handle timers...
	subi	%r4,%r4,RAVEN_TIMER_VEC_FIRST
	loadi	%r6,RAVEN_INTREG_OFF-RAVEN_INTTIMER_OFF
	sub		%r5,%r5,%r6
	b		2f
1:
	cmplwi	%r4,RAVEN_IPI_VEC_FIRST
	blt		2f
	# handle ipis...
	subi	%r4,%r4,RAVEN_IPI_VEC_FIRST
	loadi	%r6,RAVEN_INTREG_OFF-RAVEN_INTIPI_OFF
	sub		%r5,%r5,%r6
	slwi	%r6,%r4,4	# IPI vector registers separated by 0x10
	b		3f
2:
	slwi	%r6,%r4,RAVEN_INT_REGOFF_SFT
3:
	lwzx	%r7,%r5,%r6
	eieio
	ori		%r7,%r7,0x80
	stwx	%r7,%r5,%r6
	eieio
	
	li	%r3,0
	blr
CALLOUT_END	interrupt_mask_raven_mpic

#
# void interrupt_config(struct syspage_entry *sysp, level *llp, int intr)
#
# Return special config for the passed hardware interrupt number.
#
CALLOUT_START	interrupt_config_raven_mpic, 0, 0
	li		%r3,0
	cmpwi	%r5,RAVEN_IPI_VEC_FIRST
	bne		1f
	ori		%r3,%r3,INTR_CONFIG_FLAG_IPI|INTR_CONFIG_FLAG_DISALLOWED
1:
	blr
CALLOUT_END	interrupt_config_raven_mpic