epic.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


#include "startup.h"
#include "epic.h"


paddr_t	epic_base;

void
config_epic(paddr_t epic_base_addr){
uint32_t 	val,
            i,
            j;
uintptr_t 	epic;


	epic_base = epic_base_addr;
	epic = startup_io_map(MEG(1),epic_base_addr);

	// Program the cfg register to enable cascade mode
	out32(epic+EPIC_GLOBAL_CFG_REG,0x20);
	// Set the spurious value to 0xff in case it changed
	out32(epic+EPIC_SPURIOUS_REG,0xff << 24);
		// serial interrupt mode
	out32(epic+EPIC_INT_CFG, in32(epic+EPIC_INT_CFG)|0x28);

	/*
	 * program the 16 interrupts
	 * All are program level/low/masked
     * This code may need to be changed depending on hardware configuration
     * i.e. interrupts may require different polarity/trigger.  This can be 
     * overidden in the board specific init_intrinfo.c after the call
     * to config_epic().
	 */

	i = epic+EPIC_INTREG_BASE;

	for(j = 0, i += j * EPIC_INT_REG_OFF; j < 16; j ++) {
		val = 0x80 | j << 24 | ((16 - 1 - j) << 8)
			| (0x40 << 8);

		/* special case for interrupt 15; we don't want a priority of 0  */
        /* (interrupt disabled), so we set it to 1.                      */

		if (j == 15)
			val |= 1 << 8;
		out32(i, val);
		/* Program dst register to target CPU 0 only  */

 		out32(i + EPIC_INT_DST_OFF, 0x01<<24);
		i += EPIC_INT_REG_OFF;
	}

	/*
     * Program DUARTS Interrupts  (2 interrupt, 16-17)
	 *
     */

	i = epic+EPIC_DUART_INTREG_BASE;

	for(j=0;j<2;j++) {
		out32(i+(EPIC_INT_REG_OFF *j),(0x00000f80 | (0x10 + j)<<24)); /* prio 15,vector 16+j,masked */
		out32(i+(EPIC_INT_REG_OFF*j) + EPIC_INT_DST_OFF,0x01 << 24);
	}


	/*
     * Program TIMER Interrupts (4 interrupt, 18-21)
	 *
     */

	i = epic+EPIC_TIMER_INTREG_BASE;

	for(j=0;j<4;j++) {
		out32(i+(EPIC_TIMER_INT_REG_OFF *j),(0x00000f80 | (0x12 + j)<<24)); //prio 15,vector 18+j,masked
		out32(i+(EPIC_TIMER_INT_REG_OFF*j) + EPIC_INT_DST_OFF,0x01 << 24);
	}

	/*
     * Program DMA and I2C Interrupts (3 interrupt, 22-24)
	 *
     */

	i = epic+EPIC_I2CDMA_INTREG_BASE;

	for(j=0;j<3;j++) {
		out32(i+(EPIC_INT_REG_OFF *j),(0x00000f80 | (0x16 + j)<<24)); //prio 15,vector 22+j,masked
		out32(i+(EPIC_INT_REG_OFF*j) + EPIC_INT_DST_OFF,0x01 << 24);
	}


	/*
     * Program MSG Interrupts (1 interrupt, 25)
	 *
     */

	i = epic+EPIC_MSG_INTREG_BASE;

	for(j=0;j<1;j++) {
		out32(i+(EPIC_INT_REG_OFF *j),(0x00000f80 | (0x19 + j)<<24)); //prio 15,vector 25+j,masked
		out32(i+(EPIC_INT_REG_OFF*j) + EPIC_INT_DST_OFF,0x01 << 24);
	}

	out32(epic+EPIC_TASKPRIO_0,0);
		
	startup_io_unmap(epic);

}