raven.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


#include "startup.h"
#include "raven.h"

#define PIB_8259M0		0x20
#define PIB_8259M1		0x21
#define PIB_8259S0		0xa0
#define PIB_8259S1		0xa1

#define PIB_8259M_VEC	0x00
#define PIB_8259S_VEC	0x08

paddr_t	raven_mpic_base;
paddr_t raven_pib_base;

void
config_raven(paddr_t raven_mpic, paddr_t raven_pib) {
	uintptr_t	pib;
	uintptr_t	mpic;
	unsigned 	i, j, val, pol;

	raven_mpic_base = raven_mpic;
	raven_pib_base = raven_pib;
	// init PIB 8259s
	/* 1 */
	pib = startup_io_map(0x100, raven_pib);
	out8(pib + PIB_8259M0, 0x11);	// ICW1
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259M1, PIB_8259M_VEC);	// ICW2
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259M1, 0x4);	// ICW3
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259M1, 0x1);	// ICW4
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259M1, 0xfb);	// OCW1
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259M0, 0x08);	// OCW3

	/* 2 */
	out8(pib + PIB_8259S0, 0x11);	// ICW1
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259S1, PIB_8259S_VEC);	// ICW2
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259S1, 0x2);	// ICW3
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259S1, 0x1);	// ICW4
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259S1, 0xff);	// OCW1
	ppc_sync(); ppc_sync();
	out8(pib + PIB_8259S0, 0x08);	// OCW3
	startup_io_unmap(pib);

	// disable pci interrupts and setup IPI's 
	mpic = startup_io_map(MEG(1), raven_mpic);

	// Program the cfg register to enable cascade mode, no tie mode
	out32(mpic + RAVEN_CFG_REG, 0x20);

	i = mpic + RAVEN_INT_REG_START;
	pol = 0x80;
	for(j = 0; j < RAVEN_INT_NUM; ++j) {
		val = 0x80 | (j << 24) | ((RAVEN_INT_NUM - 1 - j) << 8) | (pol << 8) | (0x40 << 8);
		out32(i + RAVEN_INT_VEC_OFF, val);
		if((j == 0) || (lsp.syspage.p->num_cpu == 1)) {
			// IRQ0 ("ISA" interrupt) always goes to same CPU, or if
			// only 1 CPU, program dst register to target CPU 0 only
			out32(i + RAVEN_INT_DST_OFF, 0x01 << 24);
		} else {
			// Program dst register to target CPU 0 and 1
			out32(i + RAVEN_INT_DST_OFF, 0x03 << 24);
		}
		i += RAVEN_INT_REG_SPACING;
		pol = 0; // IRQ 0 is the only one that is pos. polarity
	}

	// Set up IPI's. Numbered 16=>19, prio from 15 to 12
	i = mpic + RAVEN_IPI_REG_START;
	for(j = 0; j < RAVEN_IPI_NUM; j ++) {
		val = ((15 - j) << 8) | ((RAVEN_INT_NUM) << 24); 
		out32(i + RAVEN_IPI_VEC_OFF, val);
		i += RAVEN_IPI_REG_SPACING;
	}

	// Program Raven timer interrupts; numbered 20=>23
	i = mpic + RAVEN_TIMER_REG_START;
	for(j = 0; j < RAVEN_TIMER_NUM; j ++) {
		val = 0x80 | ((12 - j) << 8) | ((RAVEN_INT_NUM+RAVEN_IPI_NUM + j) << 24);
		out32(i + RAVEN_TIMER_VEC_OFF, val);
		out32(i + RAVEN_INT_DST_OFF, 0x01 << 24);
		i += RAVEN_TIMER_REG_SPACING;
	}

	// Program task prio regs 
	out32(mpic + RAVEN_TASKPRIO_0, 0x00);
	// Prio 0 for CPU1, for IPI's
	out32(mpic + RAVEN_TASKPRIO_1, 0x00);

	startup_io_unmap(mpic);
}