ppc600_fpu.s

qnx powerpc MPC8245的 BSP源文件

#  
# Copyright 2007, QNX Software Systems. 
#  
# Licensed under the Apache License, Version 2.0 (the "License"). You 
# may not reproduce, modify or distribute this software except in 
# compliance with the License. You may obtain a copy of the License 
# at: http://www.apache.org/licenses/LICENSE-2.0 
#  
# Unless required by applicable law or agreed to in writing, software 
# distributed under the License is distributed on an "AS IS" basis, 
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
# 
# This file may contain contributions from others, either as 
# contributors under the License or as licensors under other terms.  
# Please review this entire file for other proprietary rights or license 
# notices, as well as the QNX Development Suite License Guide at 
# http://licensing.qnx.com/license-guide/ for other information.
# 
	.include "ppc/util.ah"

#
# Used to figure out if this PPC has an on-board FPU (used for 603e/EC603e
# identification). We install a fault handler for the FPU exception, and
# try to execute a floating point op. Also handles 82xx series, which has
# floating point registers, but can't do floating point arithmetic
# 
#

.balign	8
test_load:
	.double	0.0

fault_handler:
	mfsrr0		%r4
	addi		%r4,%r4,4
	mtsrr0		%r4
	mr			%r3,%r0
	rfi
fault_handler_end:
	
.set	FPU_EXC,0x800

routine_start ppc600_has_fpu, 1

	# install program fault handler
	
	lis		%r12,fault_handler@ha
	la		%r12,fault_handler@l(%r12)
	lswi	%r3,%r12,fault_handler_end - fault_handler
	li		%r12,FPU_EXC
	stswi	%r3,%r12,fault_handler_end - fault_handler
	addi	%r3,%r12,16
	dcbst	0,%r12
	dcbst	0,%r3
	sync
	icbi	0,%r12
	icbi	0,%r3
	isync
	
	# Set the FPU available opcode in the MSR
	mfmsr	%r4
	nop
	ori		%r4,%r4,0x2000
	mtmsr	%r4
	isync
	
   	# assume we have full floating point support
	li		%r3,2
	
	# Execute an FP load
	li		%r0,0
	lis		%r12,test_load@ha
	lfd		%f0,test_load@l(%r12)
	
	cmplwi	%r3,0
	beq		1f
	
   	# Execute an FP operation
   	li		%r0,1
	fadd	%f0,%f0,%f0

1:
	# Reset bit in MSR
	mfmsr	%r4
	li		%r5,0x2000			
	andc	%r4,%r4,%r5
	mtmsr	%r4
	isync
	
	blr
routine_end ppc600_has_fpu