callout_interrupt_raven_pib.s

qnx powerpc MPC8245的 BSP源文件

#  
# Copyright 2007, QNX Software Systems. 
#  
# Licensed under the Apache License, Version 2.0 (the "License"). You 
# may not reproduce, modify or distribute this software except in 
# compliance with the License. You may obtain a copy of the License 
# at: http://www.apache.org/licenses/LICENSE-2.0 
#  
# Unless required by applicable law or agreed to in writing, software 
# distributed under the License is distributed on an "AS IS" basis, 
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
# 
# This file may contain contributions from others, either as 
# contributors under the License or as licensors under other terms.  
# Please review this entire file for other proprietary rights or license 
# notices, as well as the QNX Development Suite License Guide at 
# http://licensing.qnx.com/license-guide/ for other information.
# 
# An entry point for a hardware kernel callout.
# It may be called by an interrupt handler.
# This code MUST be position independant.
#

	.include "callout.ah"
#
# Interrupts are always off in this code.
#
# Note that interrupt_id_* and interrupt_eoi_* are not actually
# called by the kernel. For performance reasons, they are instead
# copied into place and intermixed with other kernel code. As such,
# they don't follow normal calling conventions. They should just fall out 
# their bottoms when done rather than attempting to do a return 
# instruction. The 'id' routine should return the interrupt level in
# the r14 register. The 'eoi' routine will find it still there. 
# By turning on various INTR_GENFLAG_* bits in the intrinfo_entry,
# the following values can be loaded before entry to this code.
# 
#		cpu number			=> r15
#		syspage_ptr			=> r16
#		intrinfo_entry		=> r17
#		intr mask count		=> r18 (only available in EOI routine)
#
# If the INTR_FLAG_CPU_FAULT bit is on, the eoi routine should set
# the R3 register to the following value to indicate the exception
# that has occurred:
# 		R3 = (fault_number << 16) | (signal_code << 8) | (signal_number)
# Set R3 to zero if no exception has occured. If the exception is memory
# related, set R4 to referenced address that caused the exception, zero
# if there is no address.
#

.set RAVEN_PCI_INTACK,	0xfeff0030

.set PIB_8259M0_OFF,		0x20
.set PIB_8259M1_OFF,		0x21
.set PIB_8259S0_OFF,		0xa0
.set PIB_8259S1_OFF,		0xa1
.set PIB_MAPPING_SIZE,		0x100

# R3: syspage paddr
# R4: syspage vaddr
# R5: rtn offset
# R6: r/w offset
# R7: patch data
# R8: rtn src

patcher_id:
	stwu	%r1,-32(%r1)
	mflr	%r0
	stw		%r31,28(%r1)
	stw		%r0,36(%r1)
	
	add		%r31,%r3,%r5
	
.ifdef VARIANT_64
	li		%r5,0
	loadi	%r6,RAVEN_PCI_INTACK
.else
	loadi	%r4,RAVEN_PCI_INTACK
.endif
	loadi	%r3,4
	bl		callout_io_map

	sth		%r3,6(%r31)
	srwi	%r3,%r3,16
	sth		%r3,2(%r31)
	
	lwz		%r0,36(%r1)
	mtlr	%r0
	lwz		%r31,28(%r1)
	addi	%r1,%r1,32
	blr

patcher:
	stwu	%r1,-32(%r1)
	mflr	%r0
	stw		%r31,28(%r1)
	stw		%r0,36(%r1)
	
	add		%r31,%r3,%r5
	
   	la		%r4,raven_pib_base@sdarel(%r13)
	loadi	%r3,PIB_MAPPING_SIZE
	bl		callout_io_map_indirect

	lhz		%r4,6(%r31)
	lhz		%r5,2(%r31)
	slwi	%r5,%r5,16
	or		%r4,%r4,%r5
	add		%r3,%r3,%r4
	sth		%r3,6(%r31)
	srwi	%r3,%r3,16
	sth		%r3,2(%r31)
	
	lwz		%r0,36(%r1)
	mtlr	%r0
	lwz		%r31,28(%r1)
	addi	%r1,%r1,32
	blr

.macro DEVBASE reg,base_paddr
	# the instruction imediate values are patched by the above routine
	lis	&reg,(&base_paddr) >> 16
	ori	&reg,&reg,(&base_paddr) & 0xffff
.endm
		
# 
# int interrupt_id(void)
#
# Returns: interrupt level, masks it off
#
CALLOUT_START	interrupt_id_raven_pib, 0, patcher_id
	# The offset values of these two instructions are modified
	# by the 'patcher_id' routine above.
	lis		%r5, 0
	lbz		%r14,0(%r5)			# ack int & get vector
	eieio
CALLOUT_END	interrupt_id_raven_pib
		

# 
# void interrupt_eoi(struct syspage_entry *sysp, int intr)
#
# Send an end-of-interrupt, then unmask the level (interrupt_id masked it)
#
CALLOUT_START	interrupt_eoi_raven_pib, 0, patcher
	DEVBASE %r5, 0
	
	li		%r6,0x20
	#eoi master
	stb		%r6,PIB_8259M0_OFF(%r5)
	eieio
	
	cmplwi	%r14,8
	blt		2f			
	#eoi slave
	stb		%r6,PIB_8259S0_OFF(%r5)
	eieio
2:		
CALLOUT_END	interrupt_eoi_raven_pib


#
# int interrupt_unmask(struct syspage_entry *sysp, int intr)
#
# Unmask the passed hardware interrupt number.
#
CALLOUT_START	interrupt_unmask_raven_pib, 0, patcher
	DEVBASE %r5, PIB_8259M1_OFF

	# write memory image IMR 
	cmplwi 	%r4,8
	blt		1f
	subi	%r4,%r4,8	
	addi	%r5,%r5,PIB_8259S1_OFF-PIB_8259M1_OFF	# get 8259-2 OCW1 base
1:
	li		%r6,1
	slw		%r6,%r6,%r4
	lbz		%r0,0(%r5)
	eieio
	andc	%r0,%r0,%r6
	stb		%r0,0(%r5)		
	eieio
	
	li		%r3,0
	blr
CALLOUT_END	interrupt_unmask_raven_pib
	
#
# void interrupt_mask(struct syspage_entry *sysp, int intr)
#
# Mask the passed hardware interrupt number.
#
CALLOUT_START	interrupt_mask_raven_pib, 0, patcher
	DEVBASE %r5, PIB_8259M1_OFF

	# write memory image IMR 
	cmplwi 	%r4,8
	blt		1f
	subi	%r4,%r4,8	
	addi	%r5,%r5,PIB_8259S1_OFF-PIB_8259M1_OFF	# get 8259-2 OCW1 base
1:
	li		%r6,1
	slw		%r6,%r6,%r4
	lbz		%r0,0(%r5)
	eieio
	or		%r0,%r0,%r6
	stb		%r0,0(%r5)		
	eieio
	
	li		%r3,0
	blr
CALLOUT_END	interrupt_mask_raven_pib