ppc440gx_set_clock_freqs.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */



/*
 * ppc440gx_set_clock_freqs.c
 * Set the cpu_freq, cycles_freq, and timer_freq variables, based on
 * the main system clock
 *
 */

#include "startup.h"
#include <ppc/440cpu.h>

unsigned long ppc4xx_opbclock;

void
ppc440gx_set_clock_freqs(unsigned sys_clk) {
	unsigned	strp0, strp1;
	unsigned	temp;
	unsigned	lfdv;
	unsigned	fbdv;
	unsigned	fwdva;
	unsigned	fwdvb;
	unsigned	opbdv;
	unsigned	ebdv;
	unsigned	core_clock;
	unsigned	m;

	get_sdr(PPC440GX_SDR0_SDSTP0, strp0)
	get_sdr(PPC440GX_SDR0_SDSTP1, strp1)

	fwdva = (strp0 & PPC440GX_SDR0_SDSTP0_FWDVA_MASK) >> PPC440GX_SDR0_SDSTP0_FWDVA_SHIFT;
	if (!fwdva) fwdva = 16;
	fwdvb = (strp0 & PPC440GX_SDR0_SDSTP0_FWDVB_MASK) >> PPC440GX_SDR0_SDSTP0_FWDVB_SHIFT;
	if (!fwdva) fwdvb = 8;
	fbdv = (strp0 & PPC440GX_SDR0_SDSTP0_FBDV_MASK) >> PPC440GX_SDR0_SDSTP0_FBDV_SHIFT;
	if (!fbdv) fbdv = 32;
	opbdv = (strp0 & PPC440GX_SDR0_SDSTP0_OPBDV0_MASK) >> PPC440GX_SDR0_SDSTP0_OPBDV0_SHIFT;
	if (!opbdv) opbdv = 4;
	ebdv = (strp1 & PPC440GX_SDR0_SDSTP1_PERDV0_MASK) >> PPC440GX_SDR0_SDSTP1_PERDV0_SHIFT;
	if (!ebdv) ebdv = 4;

	temp = (strp0 & PPC440GX_SDR0_SDSTP0_SEL_MASK) >> PPC440GX_SDR0_SDSTP0_SEL_SHIFT;
	lfdv = (strp1 & PPC440GX_SDR0_SDSTP1_LFBDV_MASK) >> PPC440GX_SDR0_SDSTP1_LFBDV_SHIFT;
	if (!lfdv) lfdv = 64;

	if (temp == 0) {
		temp = (strp0 & PPC440GX_SDR0_SDSTP0_SRC_MASK) >> PPC440GX_SDR0_SDSTP0_SRC_SHIFT;
		if (!temp)
			m = fbdv * lfdv * fwdva;
		else
			m = fbdv * lfdv * fwdvb;
	}
	else if (temp == 1)
		m = fbdv * fwdvb;
	else
		m = ebdv * opbdv * fwdvb;

	temp = ((m * sys_clk) + (m >> 1));
	ppc4xx_opbclock = temp / (fwdvb * opbdv);
	core_clock = temp / fwdva;
	if (cpu_freq == 0)
		cpu_freq = core_clock;
	if (timer_freq == 0) {
		temp = get_spr(PPC440_SPR_CCR1);
		if (temp & PPC440_CCR1_TCS)	/* Timer clock selected */
			timer_freq = 25000000;	/* Default */
		else
			timer_freq = core_clock;
	}
	if (cycles_freq == 0)
		cycles_freq = timer_freq;
}