gt64260.h

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


#define DISCOVERY_NUM_INTR_64260    	64
#define DISCOVERY_NUM_INTR_GPP      	32

#define GT64260_DMA2                	0x0818
#define GT64260_DMA3                	0x081c
#define GT64260_CPU_CTRL            	0x160
#define GT64260_CPUMASK_LO          	0xc1c
#define GT64260_CPUMASK_HI          	0xc6c
#define GT64260_CPU_SELECTCAUSE     	0xc70
#define GT64260_PCI0MASK_LO          	0xc24
#define GT64260_PCI0MASK_HI          	0xc64
#define GT64260_PCI0_SELECTCAUSE     	0xc74
#define GT64260_PCI1MASK_LO          	0xca4
#define GT64260_PCI1MASK_HI          	0xce4
#define GT64260_PCI1_SELECTCAUSE     	0xcf4
#define GT64260_GPP_IOCTL           	0xf100
#define GT64260_GPP_LEVEL           	0xf110
#define GT64260_GPP_VALUE           	0xf104
#define GT64260_GPP_CAUSE           	0xf108
#define GT64260_GPP_MASK            	0xf10c

#define PCI0_SNOOP_CONTROL0_BASE_LOW    0x1f00
#define PCI0_SNOOP_CONTROL0_BASE_HI     0x1f04
#define PCI0_SNOOP_CONTROL0_TOP         0x1f08

#define PCI1_SNOOP_CONTROL0_BASE_LOW    0x1f80
#define PCI1_SNOOP_CONTROL0_BASE_HI     0x1f84
#define PCI1_SNOOP_CONTROL0_TOP         0x1f88


#define GT64260_P2P0_CNFG       0x1d14
#define GT64260_P2P1_CNFG       0x1d94

#define GT64260_PCI0_ADDR       0xcf8
#define GT64260_PCI0_DATA       0xcfc
#define GT64260_PCI1_ADDR       0xc78
#define GT64260_PCI1_DATA       0xc7c

#define GT64260_COMM_ARBIT		0xf300

#define MPP_CTRL_0			0xf000
#define MPP_CTRL_1			0xf004
#define MPP_CTRL_2			0xf008
#define MPP_CTRL_3			0xf00c

extern struct callout_rtn   interrupt_mask_gt64260;
extern struct callout_rtn   interrupt_unmask_gt64260;
extern struct callout_rtn   interrupt_id_gt64260;
extern struct callout_rtn   interrupt_eoi_gt64260;
extern struct callout_rtn   interrupt_config_gt64260;

extern struct callout_rtn   interrupt_mask_gt64260pi;
extern struct callout_rtn   interrupt_unmask_gt64260ipi;

extern struct callout_rtn   interrupt_mask_gt64260timer;
extern struct callout_rtn   interrupt_unmask_gt64260timer;

extern void gt64260_init_raminfo(unsigned long);

extern paddr_t  gt64260_base;


#define GT64260_INTRS(first_intr) \
	{   first_intr, DISCOVERY_NUM_INTR_64260+DISCOVERY_NUM_INTR_GPP,_NTO_INTR_SPARE, PPC_EXC_EXTERNAL_INTR, 0, 0,	\
    {INTR_GENFLAG_LOAD_CPUNUM, 0, &interrupt_id_gt64260},															\
    {INTR_GENFLAG_LOAD_INTRMASK, 0, &interrupt_eoi_gt64260},														\
    &interrupt_mask_gt64260, &interrupt_unmask_gt64260,		 														\
	&interrupt_config_gt64260,																						\
    &gt64260_base,																									\
	},