ppc8260_set_clock_freqs.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


#include "startup.h"
#include <ppc/8260cpu.h>

struct corecnf_t {
	int	b2c_mult2;
	int	vco_div;
};

static struct corecnf_t corecnf_table[] = {
	{  3,  4 },    /* 0x00 */
	{  2,  4 },    /* 0x01 */
	{  2,  8 },    /* 0x02 */
	{ -1, -1 },    /* 0x03 */
	{  2,  2 },    /* 0x04 */
	{  4,  4 },    /* 0x05 */
	{  5,  2 },    /* 0x06 */
	{  9,  2 },    /* 0x07 */
	{  6,  2 },    /* 0x08 */
	{ 11,  2 },    /* 0x09 */
	{  8,  2 },    /* 0x0A */
	{ 10,  2 },    /* 0x0B */
	{  3,  8 },    /* 0x0C */
	{ 12,  2 },    /* 0x0D */
	{  7,  2 },    /* 0x0E */
	{ -1, -1 },    /* 0x0F */
	{  6,  4 },    /* 0x10 */
	{  5,  4 },    /* 0x11 */
	{ 11,  2 },    /* 0x12 */
	{ -1, -1 },    /* 0x13 */
	{ 14,  2 },    /* 0x14 */
	{  4,  4 },    /* 0x15 */
	{ 15,  2 },    /* 0x16 */
	{  9,  2 },    /* 0x17 */
	{ -1, -1 },    /* 0x18 */
	{ 11,  2 },    /* 0x19 */
	{  8,  2 },    /* 0x1A */
	{ 10,  2 },    /* 0x1B */
	{ 16,  2 },    /* 0x1C */
	{ 12,  2 },    /* 0x1D */
	{  7,  2 },    /* 0x1E */
	{ -1, -1 },    /* 0x1F */
};

#define	PPC8260_HIP7		0x80822011
#define	PPC8260_HIP7R1		0x80822013
#define PPC8260_HIP7A0		0x80822014

uint32_t	ppc8260_brgclk;
/*
uint32_t	ppc8260_cpmclk;
uint32_t	ppc8260_sccclk;
*/

void ppc8260_set_clock_freqs(unsigned inputclk)
{
	uint32_t	dfbrg, scmr, busdf, cpmdf, pllmf, plldf, vco_out;
	uint32_t	cpu_clk;
	int			corecnf;
	uintptr_t	pv_immr_base_addr = startup_io_map(0x14000, immr_paddr);

	if (cycles_freq == 0)
		cycles_freq = timer_freq = inputclk >> 2;

	dfbrg = in32(pv_immr_base_addr + PPC8260_IMMR_OFF_SCCR) & PPC8260_SCCR_DFBRG_MASK;
	scmr = in32(pv_immr_base_addr + PPC8260_IMMR_OFF_SCMR);
	busdf = (scmr & PPC8260_SCMR_BUSDF_MASK) >> PPC8260_SCMR_BUSDF_SHIFT;
	cpmdf = (scmr & PPC8260_SCMR_CPMDF_MASK) >> PPC8260_SCMR_CPMDF_SHIFT;
	corecnf = (scmr & PPC8260_SCMR_CORECNF_MASK) >> PPC8260_SCMR_CORECNF_SHIFT;

	switch (get_pvr()) {
		/* HIP7 silicon */
		case PPC8260_HIP7:
		case PPC8260_HIP7R1:
		case PPC8260_HIP7A0:
			pllmf = (scmr & PPC8260_SCMR_PLLMF_MASKHIP7) >> PPC8260_SCMR_PLLMF_SHIFT;
			vco_out = inputclk * (pllmf + 1);
			break;
		default:    /* HIP4, HIP3 silicon */
			pllmf = (scmr & PPC8260_SCMR_PLLMF_MASK) >> PPC8260_SCMR_PLLMF_SHIFT;
			plldf = (scmr & PPC8260_SCMR_PLLDF) ? 1 : 0;
			vco_out = (inputclk * 2 * (pllmf + 1)) / (plldf + 1);
			break;
	}

#if 0
	ppc8260_cpmclk = vco_out >> 1;
	ppc8260_sccclk = vco_out >> 2;
#endif
	ppc8260_brgclk = vco_out / (1 << ((dfbrg + 1) << 1));

	cpu_clk = inputclk;
	if (corecnf_table[corecnf].b2c_mult2 > 0)
		cpu_clk = (cpu_clk * corecnf_table[corecnf].b2c_mult2) >> 1;

	if (cpu_freq == 0) 
		cpu_freq = cpu_clk;

	startup_io_unmap(pv_immr_base_addr);
}