callout_sendipi_raven.s

qnx powerpc MPC8245的 BSP源文件

#  
# Copyright 2007, QNX Software Systems. 
#  
# Licensed under the Apache License, Version 2.0 (the "License"). You 
# may not reproduce, modify or distribute this software except in 
# compliance with the License. You may obtain a copy of the License 
# at: http://www.apache.org/licenses/LICENSE-2.0 
#  
# Unless required by applicable law or agreed to in writing, software 
# distributed under the License is distributed on an "AS IS" basis, 
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
# 
# This file may contain contributions from others, either as 
# contributors under the License or as licensors under other terms.  
# Please review this entire file for other proprietary rights or license 
# notices, as well as the QNX Development Suite License Guide at 
# http://licensing.qnx.com/license-guide/ for other information.
# 
# An entry point for a hardware kernel callout.
# It may be called by an interrupt handler.
# This code MUST be position independant.
#

	.include "callout.ah"
	
	.extern		raven_mpic_base

# R3: syspage paddr
# R4: syspage vaddr
# R5: rtn offset
# R6: r/w offset
# R7: patch data
# R8: rtn src

patcher:
	stwu	%r1,-32(%r1)
	mflr	%r0
	stw		%r31,28(%r1)
	stw		%r0,36(%r1)
	
	add		%r31,%r3,%r5
	
	la		%r4,raven_mpic_base@sdarel(%r13)
	loadi	%r3,0x10000
	bl		callout_io_map_indirect

	lhz		%r4,6(%r31)
	lhz		%r5,2(%r31)
	slwi	%r5,%r5,16
	or		%r4,%r4,%r5
	add		%r3,%r3,%r4
	sth		%r3,6(%r31)
	srwi	%r3,%r3,16
	sth		%r3,2(%r31)
	
	lwz		%r0,36(%r1)
	mtlr	%r0
	lwz		%r31,28(%r1)
	addi	%r1,%r1,32
	blr

.macro DEVBASE reg,dev_reg_off
	# the instruction immediate values are patched by the above routine
	lis		&reg,(&dev_reg_off) >> 16
	ori		&reg,&reg,(&dev_reg_off) & 0xffff
.endm

		
CALLOUT_START	sendipi_raven, 0, patcher
	DEVBASE		%r7,0x20040		# IPI dispatch register offset
#
# Send an IPI
#
#
# %r3: syspage ptr
# %r4: cpunum
# %r5: ipi code 	
# %r6: &ipicmds
#

	rlwinm 	%r4,%r4,0,31,31
	
	# Compute address of registers
	
	# Since we never send an IPI to ourselves, and the raven chip
	# only supports two CPUs, we're running on the opposite CPU
	# that the IPI is going to.
	xori	%r10,%r4,1
	slwi 	%r10,%r10,12

	# Disable interrupts
	loadi	%r9,PPC_MSR_EE
	mfmsr	%r8
	andc	%r9,%r8,%r9
	mtmsr	%r9

2:
	lwarx	%r3,0,%r6
	or		%r3,%r3,%r5
	stwcx.	%r3,0,%r6
	bne-	2b

	li 		%r0,1
	slw 	%r0,%r0,%r4
	slwi 	%r0,%r0,24
	stwx 	%r0,%r7,%r10
	eieio

	mtmsr	%r8
	blr
CALLOUT_END		sendipi_raven