ppc85xx_set_clock_freqs.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */

/*
 * ppc85xx_set_clock_freqs.c
 * Set the cpu_freq, cycles_freq, and timer_freq variables, based on
 * the main system clock
 *
 */

#include "startup.h"
#include <ppc/85xxcpu.h>
#include <ppc/8260cpu.h>


extern uint32_t ppc8260_brgclk;

void
ppc85xx_set_get_clock_freqs(unsigned sys_clk, unsigned rtc, 
						unsigned *platform_p, unsigned *core_p) {

	unsigned 	platform_clock;
	unsigned 	core_clock;
	unsigned	pll;
	uintptr_t	base;
	uint32_t 	dfbrg;

	base = startup_io_map(MEG(1), immr_paddr);

	pll = in32(base + PPC85xx_CCSR_OFF_PORPLLSR);

	//NYI: BYPASS: Which PLL does it bypass, E500 or platform?

	platform_clock = sys_clk * ((pll & PPC85xx_PORPLLSR_PLAT_MASK) >> PPC85xx_PORPLLSR_PLAT_SHIFT);
	core_clock = (platform_clock * ((pll & PPC85xx_PORPLLSR_E500_MASK) >> PPC85xx_PORPLLSR_E500_SHIFT))/2;

	if(cpu_freq == 0) {
		cpu_freq = core_clock;
	}

	if(!(get_spr(PPCE500_SPR_HID0) & PPCE500_HID0_SEL_TBCLK)) {
		rtc = platform_clock / 8;
	}
	if(timer_freq == 0)  timer_freq  = rtc;
	if(cycles_freq == 0) cycles_freq = rtc;

	dfbrg = in32(base + cpm_offset +  PPC8260_IMMR_OFF_SCCR) & PPC8260_SCCR_DFBRG_MASK;

	/* VCO_OUT is twice the platform clock. Set BRG clk so that 8260
	debug callout can pick up the correct clock rate. */
	ppc8260_brgclk = (platform_clock*2) / (1 << ((dfbrg + 1) << 1));

	startup_io_unmap(base);

	if (platform_p != NULL) {
		*platform_p = platform_clock;
	}
	if (core_p != NULL) {
		*core_p = core_clock;
	}
}


void
ppc85xx_set_clock_freqs(unsigned sys_clk, unsigned rtc) {

	ppc85xx_set_get_clock_freqs(sys_clk, rtc, NULL, NULL);

}