ppcv_cpuconfig_600.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */

#include "startup.h"

static void
init_stuff(cpu) {
	unsigned 	spr_hid0;

	if(shdr->flags1 & STARTUP_HDR_FLAGS1_VIRTUAL) {
		ppcv_mmuconfig1_600(cpu);
	}

	// Flush caches for startup
	ppc_sync();
	spr_hid0 = get_spr(PPC603_SPR_HID0);

	if(!(spr_hid0 & PPC603_SPR_HID0_ICE)) {
		// Turn on I-cache
		spr_hid0 |= PPC603_SPR_HID0_ICE;
		set_spr(PPC603_SPR_HID0, spr_hid0);
		ppc_sync(); ppc_isync();

		// Flush it
		set_spr(PPC603_SPR_HID0, spr_hid0 | PPC603_SPR_HID0_ICFI);
		ppc_sync(); ppc_isync();

		set_spr(PPC603_SPR_HID0, spr_hid0);
		ppc_sync(); ppc_isync();
	}

	if(!(spr_hid0 & PPC603_SPR_HID0_DCE)) {
		unsigned i;

		// If the data cache isn't on yet, turn it on.
		spr_hid0 |= PPC603_SPR_HID0_DCE;
		ppc_sync();
		set_spr(PPC603_SPR_HID0, spr_hid0 | PPC603_SPR_HID0_DCFI);
		for(i = 0; i < 0x1000; ++i ) { /*small delay*/ }
		set_spr(PPC603_SPR_HID0, spr_hid0);
		ppc_sync(); ppc_isync();
	}
}
	
void
ppcv_cpuconfig1_600(int cpu) {

	// Point exception table at bottom of memory
	set_msr(get_msr() & ~PPC_MSR_EP);

	init_stuff(cpu);
}

void
ppcv_cpuconfig2_600(int cpu) {
	unsigned	hid0;

	hid0 = get_spr(PPC603_SPR_HID0);
	if(lsp.syspage.p->num_cpu > 1) {
		extern void ppc600_set_pir(unsigned);

		hid0 |= PPC700_SPR_HID0_ABE;

		// The PPC has a PIR register to hold the CPU number, but the 7xx
		// chips didn't implement that register for some reason, even though
		// they're capable of being used in an SMP system (they shouldn't
		// though, since they only have MEI state caches). Anyhow, we used to
		// use the PIR SPR to hold the CPU number, so we temporary set that
		// as well, so that new startups with old procnto's continue to work
		ppc600_set_pir(cpu);
	}
	
	// Flush instruction cache.
	set_spr(PPC603_SPR_HID0, hid0 | PPC603_SPR_HID0_ICFI);
	ppc_sync(); ppc_isync();

	set_spr(PPC603_SPR_HID0, hid0);
	ppc_sync(); ppc_isync();

	if(paddr_bits > 32) {
		/*
		 * Turn on XAE -- we need to do the following first:
		 * Inval cache, tlb, BATs
		 */
		//NYI: have to flush out/invalidate stuff here since
		//we already have translation & caches enabled
		init_stuff(cpu);

		hid0 = get_spr(PPC603_SPR_HID0);
		hid0 |= PPC7450_SPR_HID0_XAEN;
		ppc_sync(); ppc_isync();
		set_spr(PPC603_SPR_HID0, hid0);
		ppc_sync(); ppc_isync();
	}
	if(shdr->flags1 & STARTUP_HDR_FLAGS1_VIRTUAL) {
		ppcv_mmuconfig2_600(cpu);
	}
}