callout_interrupt_8260.s

qnx powerpc MPC8245的 BSP源文件

#  
# Copyright 2007, QNX Software Systems. 
#  
# Licensed under the Apache License, Version 2.0 (the "License"). You 
# may not reproduce, modify or distribute this software except in 
# compliance with the License. You may obtain a copy of the License 
# at: http://www.apache.org/licenses/LICENSE-2.0 
#  
# Unless required by applicable law or agreed to in writing, software 
# distributed under the License is distributed on an "AS IS" basis, 
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
# 
# This file may contain contributions from others, either as 
# contributors under the License or as licensors under other terms.  
# Please review this entire file for other proprietary rights or license 
# notices, as well as the QNX Development Suite License Guide at 
# http://licensing.qnx.com/license-guide/ for other information.
# 
# An entry point for a hardware kernel callout.
# It may be called by an interrupt handler.
# This code MUST be position independant.
#

	.include "callout.ah"
	.include "ppc/util.ah"
#
# Interrupts are always off in this code.
#
# Note that interrupt_id_* and interrupt_eoi_* are not actually
# called by the kernel. For performance reasons, they are instead
# copied into place and intermixed with other kernel code. As such,
# they don't follow normal calling conventions. They should just fall out 
# their bottoms when done rather than attempting to do a return 
# instruction. The 'id' routine should return the interrupt level in
# the r14 register. The 'eoi' routine will find it still there. 
# By turning on various INTR_GENFLAG_* bits in the intrinfo_entry,
# the following values can be loaded before entry to this code.
# 
#		cpu number			=> r15
#		syspage_ptr			=> r16
#		intrinfo_entry		=> r17
#		intr mask count		=> r18 (only available in EOI routine)
#
# If the INTR_FLAG_CPU_FAULT bit is on, the eoi routine should set
# the R3 register to the following value to indicate the exception
# that has occurred:
# 		R3 = (fault_number << 16) | (signal_code << 8) | (signal_number)
# Set R3 to zero if no exception has occured. If the exception is memory
# related, set R4 to referenced address that caused the exception, zero
# if there is no address.
#

patcher:
	# R3: syspage paddr
	# R4: syspage vaddr
	# R5: rtn dst offset
	# R6: r/w offset
	# R7: patch data
	# R8: rtn src

	stwu    %r1,-32(%r1)
	mflr    %r0
	stw     %r31,28(%r1)
	stw     %r0,36(%r1)

	add     %r31,%r3,%r5

	lwz     %r4,0(%r7)
	loadwz	%r3,cpm_offset
	add		%r4,%r4,%r3
	loadi   %r3,0x14000
	bl      callout_io_map

	sth     %r3,6(%r31)
	srwi    %r3,%r3,16
	sth     %r3,2(%r31)

	lwz     %r0,36(%r1)
	mtlr    %r0
	lwz     %r31,28(%r1)
	addi    %r1,%r1,32
	blr


.ifdef PPC85xx

.macro SET_MSR, reg_s, reg_t
	mfmsr	&reg_s
	loadi 	&reg_t, PPC_MSR_EE|PPC_MSR_CE|PPC_MSR_DR
	andc	&reg_t, &reg_s, &reg_t
	mtmsr	&reg_t
	isync
.endm

.macro RESTORE_MSR, reg_s
	mtmsr	&reg_s
	isync
.endm

.macro CS, pref
	CALLOUT_START &pref&_85xxcpm, 0, patcher
.endm	

.macro CE pref
	CALLOUT_END	&pref&_85xxcpm
.endm	

.else

.macro SET_MSR, reg_s, reg_t
.endm


.macro RESTORE_MSR, reg_s
.endm

.macro CS, pref
	CALLOUT_START &pref&_8260, 0, patcher
.endm	

.macro CE pref
	CALLOUT_END	&pref&_8260
.endm	

.endif

# 
# int interrupt_id(void)
#
# Returns: interrupt level, masks it off
#
CS interrupt_id
	# get id
	lis		%r5, 0x1234
	ori		%r5, %r5, 0x5678		# CPM IMMR base address (patched)

	SET_MSR	%r12, %r11

	loadi	%r8,PPC8260_IMMR_OFF_SIVEC
	lbzx	%r14,%r5,%r8
	srwi	%r14,%r14,2

	# mask interrupt		
	# later opt it to a lookup table
	cmplwi	%r14,15
	bgt		1f
	# I2C to TIMER4
	lis		%r7,0x1
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_L
	srw		%r7,%r7,%r14
	b		2f
1:
	cmplwi	%r14,18
	bgt		1f
	# TMCNT,PIT,PCI(MPC8265,MPC8266,MPC8250 only)
	subi	%r6,%r14,16
	li		%r7,0x4
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	srw		%r7,%r7,%r6
	b		2f
1:
	cmplwi	%r14,25
	bgt		1f
	# IRQ1 to IRQ7
	subi	%r6,%r14,19
	li		%r7,0x4000
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	srw		%r7,%r7,%r6
	b		2f
1:
	cmplwi	%r14,0x2C
	bgt		1f
	#FCC1 to SCC4, TC Layer(MPC8264,MPC8266 only)
	subi	%r6,%r14,0x20
	lis		%r7,0x8000
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_L
	srw		%r7,%r7,%r6
	b		2f
1:
	#PC15 to PC0
	subi	%r6,%r14,0x30
	lis		%r7,0x1
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	slw		%r7,%r7,%r6
2:
#mask it
	lwzx	%r6,%r5,%r8
	andc	%r6,%r6,%r7
	stwx	%r6,%r5,%r8

	RESTORE_MSR	%r12

CE		interrupt_id
	
# 
# void interrupt_eoi
#
# Send an end-of-interrupt, then unmask the level (interrupt_id masked it)
#
CS interrupt_eoi
	# later opt it to a lookup table
	lis		%r5, 0x1234
	ori		%r5, %r5, 0x5678		# CPM IMMR base address (patched)

	cmplwi	%r14,15
	bgt		1f

	# I2C to TIMER4
	lis		%r7,0x1
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_L
	loadi	%r9,PPC8260_IMMR_OFF_SIPNR_L
	srw		%r7,%r7,%r14
	b		2f
1:
	cmplwi	%r14,18
	bgt		1f
	# TMCNT,PIT,PCI
	subi	%r6,%r14,16
	li		%r7,0x4
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	loadi	%r9,PPC8260_IMMR_OFF_SIPNR_H
	srw		%r7,%r7,%r6
	b		2f
1:
	cmplwi	%r14,25
	bgt		1f
	# IRQ1 to IRQ7
	subi	%r6,%r14,19
	li		%r7,0x4000
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	loadi	%r9,PPC8260_IMMR_OFF_SIPNR_H
	srw		%r7,%r7,%r6
	b		2f
1:
	cmplwi	%r14,0x2C
	bgt		1f
	#FCC1 to SCC4, TC Layer
	subi	%r6,%r14,0x20
	lis		%r7,0x8000
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_L
	loadi	%r9,PPC8260_IMMR_OFF_SIPNR_L
	srw		%r7,%r7,%r6
	b		2f
1:
	#PC15 to PC0
	subi	%r6,%r14,0x30
	lis		%r7,0x1
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	loadi	%r9,PPC8260_IMMR_OFF_SIPNR_H
	slw		%r7,%r7,%r6
2:
	# eoi first
	# some sources with event registers might not need it NIY

	SET_MSR	%r12, %r11

	lwzx	%r6,%r5,%r9
	or		%r6,%r6,%r7
	stwx	%r6,%r5,%r9

	cmplwi	%r18,0
	bgt		1f

	#unmask it
	
	lwzx	%r6,%r5,%r8
	or		%r6,%r6,%r7
	stwx	%r6,%r5,%r8

1:
	RESTORE_MSR	%r12
CE		interrupt_eoi
	
		
#
# int interrupt_unmask(struct syspage_entry *sysp, int intr)
#
# Unmask the passed hardware interrupt number.
#
CS interrupt_unmask
	# later opt it to a lookup table
	lis		%r5, 0x1234
	ori		%r5, %r5, 0x5678		# CPM IMMR base address (patched)
	
	cmplwi	%r4,15
	bgt		1f

	# I2C to TIMER4
	lis		%r7,0x1
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_L
	srw		%r7,%r7,%r4
	b		2f
1:
	cmplwi	%r4,18
	bgt		1f
	# TMCNT,PIT,PCI
	subi	%r6,%r4,16
	li		%r7,0x4
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	srw		%r7,%r7,%r6
	b		2f
1:
	cmplwi	%r4,25
	bgt		1f
	# IRQ1 to IRQ7
	subi	%r6,%r4,19
	li		%r7,0x4000
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	srw		%r7,%r7,%r6
	b		2f
1:
	cmplwi	%r4,0x2C
	bgt		1f
	#FCC1 to SCC4, TC Layer
	subi	%r6,%r4,0x20
	lis		%r7,0x8000
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_L
	srw		%r7,%r7,%r6
	b		2f
1:
	#PC15 to PC0
	subi	%r6,%r4,0x30
	lis		%r7,0x1
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	slw		%r7,%r7,%r6
2:
	#unmask it
	SET_MSR	%r12, %r11
	lwzx	%r6,%r5,%r8
	or		%r6,%r6,%r7
	stwx	%r6,%r5,%r8
	RESTORE_MSR %r12

	li		%r3,0
	blr
CE		interrupt_unmask
		
#
# int interrupt_mask(struct syspage_entry *sysp, int intr)
#
# Mask the passed hardware interrupt number.
#
CS interrupt_mask
	# later opt it to a lookup table
	lis		%r5, 0x1234
	ori		%r5, %r5, 0x5678	# CPM base address (patched)
	
	cmplwi	%r4,15
	bgt		1f

	# I2C to TIMER4
	lis		%r7,0x1
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_L
	srw		%r7,%r7,%r4
	b		2f
1:
	cmplwi	%r4,18
	bgt		1f
	# TMCNT,PIT,PCI
	subi	%r6,%r4,16
	li		%r7,0x4
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	srw		%r7,%r7,%r6
	b		2f
1:
	cmplwi	%r4,25
	bgt		1f
	# IRQ1 to IRQ7
	subi	%r6,%r4,19
	li		%r7,0x4000
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	srw		%r7,%r7,%r6
	b		2f
1:
	cmplwi	%r4,0x2C
	bgt		1f
	#FCC1 to SCC4, TC Layer
	subi	%r6,%r4,0x20
	lis		%r7,0x8000
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_L
	srw		%r7,%r7,%r6
	b		2f
1:
	#PC15 to PC0
	subi	%r6,%r4,0x30
	lis		%r7,0x1
	loadi	%r8,PPC8260_IMMR_OFF_SIMR_H
	slw		%r7,%r7,%r6
2:
	#mask it
	SET_MSR	%r12, %r11
	lwzx	%r6,%r5,%r8
	andc	%r6,%r6,%r7
	stwx	%r6,%r5,%r8
	RESTORE_MSR	%r12

	li		%r3,0
	blr
CE	interrupt_mask