📄 callout_cache_ppc.s
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# # Copyright 2007, QNX Software Systems. # # Licensed under the Apache License, Version 2.0 (the "License"). You # may not reproduce, modify or distribute this software except in # compliance with the License. You may obtain a copy of the License # at: http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" basis, # WITHOUT WARRANTIES OF ANY KIND, either express or implied.# # This file may contain contributions from others, either as # contributors under the License or as licensors under other terms. # Please review this entire file for other proprietary rights or license # notices, as well as the QNX Development Suite License Guide at # http://licensing.qnx.com/license-guide/ for other information.# # This is a kernel hardware callout.# This code MUST be position independant.# .include "callout.ah"## unsigned control( paddr32_t base,# unsigned num_lines,# int flags,# struct cacheattr_entry *cache,# volatile struct syspage_entry * )## Perform the cache controller operations indicated by 'flags' # (MS_* bits passed to the msync() function).#CALLOUT_START cache_ippc, 0, 0 # Don't try to do all lines (preemption) lwz %r9,CA_LINE_SIZE(%r6) cmplwi %r4,64 ble 1f li %r4,641: mtctr %r41: icbi 0,%r3 # invalidate one line from ins cache add %r3,%r3,%r9 bdnz+ 1b mr %r3,%r4 # we did all the lines requested mod 64 isync blrCALLOUT_END cache_ippcCALLOUT_START cache_dppc, 0, 0 # Don't try to do all lines (preemption) lwz %r9,CA_LINE_SIZE(%r6) cmplwi %r4,64 ble 1f li %r4,641: mr %r8,%r3 bittst %r0,%r5,(MS_SYNC | MS_ASYNC) beq 1f mtctr %r42: dcbst 0,%r8 # Flush from data cache add %r8,%r8,%r9 bdnz+ 2b1: bittst %r0,%r5,MS_INVALIDATE beq 1f mtctr %r42: dcbi 0,%r3 # invalidate from data cache add %r3,%r3,%r9 bdnz+ 2b1: mr %r3,%r4 # we did all the lines requested mod 64 sync blrCALLOUT_END cache_dppc
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