pic_85xx.h

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */




#include <ppc/85xxintr.h>

extern struct callout_rtn   interrupt_mask_ppc85xx;
extern struct callout_rtn   interrupt_unmask_ppc85xx;
extern struct callout_rtn   interrupt_id_ppc85xx;
extern struct callout_rtn   interrupt_eoi_ppc85xx;
extern struct callout_rtn   interrupt_config_ppc85xx;

extern struct callout_rtn   interrupt_mask_ppc85xx_extnd;
extern struct callout_rtn   interrupt_unmask_ppc85xx_extnd;
extern struct callout_rtn   interrupt_id_ppc85xx_extnd;
extern struct callout_rtn   interrupt_eoi_ppc85xx_extnd;
extern struct callout_rtn   interrupt_config_ppc85xx_extnd;

extern struct callout_rtn   interrupt_mask_85xxcpm;
extern struct callout_rtn   interrupt_unmask_85xxcpm;
extern struct callout_rtn   interrupt_id_85xxcpm;
extern struct callout_rtn   interrupt_eoi_85xxcpm;

extern void ppc85xx_config_pic(void);
extern void ppc85xx_config_pic_cpm(void);

#define PPC85xx_INTRS() \
	{PPC_INTR_CLASS_85xx, 56, _NTO_INTR_SPARE, PPCBKE_SPR_IVOR4, 0, 0,	\
    {0, 0, &interrupt_id_ppc85xx},															\
    {0, 0, &interrupt_eoi_ppc85xx},														\
    &interrupt_mask_ppc85xx, &interrupt_unmask_ppc85xx,		 														\
	&interrupt_config_ppc85xx,																						\
    &immr_paddr,																									\
	},	

#define PPC85xx_INTRS_EXTND() \
	{PPC85xx_INTR_EXTND_BASE, 24, _NTO_INTR_SPARE, PPCBKE_SPR_IVOR4, 0, 0,	\
    {0, 0, &interrupt_id_ppc85xx_extnd},															\
    {0, 0, &interrupt_eoi_ppc85xx_extnd},														\
    &interrupt_mask_ppc85xx_extnd, &interrupt_unmask_ppc85xx_extnd,		 														\
	&interrupt_config_ppc85xx_extnd,																						\
    &immr_paddr,																									\
	},	


#define PPC85xx_INTRS_CPM() \
	{PPC85xx_INTR_CPM_BASE, 64, PPC85xx_INTR_CPM, 0, 0, 0,	\
    {0, 0, &interrupt_id_85xxcpm},																				\
    {INTR_GENFLAG_LOAD_INTRMASK, 0, &interrupt_eoi_85xxcpm},														\
    &interrupt_mask_85xxcpm, &interrupt_unmask_85xxcpm, 0,														\
    &immr_paddr,																									\
	},