callout_interrupt_mgt5200.s

qnx powerpc MPC8245的 BSP源文件

/*
 * clear the interrupt by writing a 1 to the appropriate bit in the status register, 
 * and unmask. r14 still holds the level.
 */
 	DEVBASE %r6, 0x12345678 

    lwz     %r5,MGT5200_GPIOSSR(%r6)               

	lis		%r4, 0x8000
	srw		%r4, %r4, %r14				/* shift the bit to the proper position */
	stw		%r4, MGT5200_GPIOSSR(%r6)					/* write appropriate bit into r6. Don't read/modify/write, */
										/* or we might clear interrupts that haven't been serviced yet */

	cmplwi	%r18, 0
	bgt		1f

	lwz 	%r5, MGT5200_GPIOSIIE(%r6)
	or      %r5,%r4,%r5             /* set bit to unmask */
	stw     %r5, MGT5200_GPIOSIIE(%r6)             /* store new value */
1:
CALLOUT_END		interrupt_eoi_mgt5200_gpio


/*************************************************************************************
 *
 * Wake-up GPIO callouts
 *
 *************************************************************************************/
/***************************************************************************
 * Callout : 	interrupt_unmask_mgt5200_gpiow
 *
 * Description: Unmask the given GPIO interrupt level
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_unmask_mgt5200_gpiow, 0, patcher

/*
 * Unmask the interrupt level that gets passed in r4. Setting a bit 
 * in the Wakeup GPIO Individual Interrupt Enable Register unmasks the interrupt.
 */
 	DEVBASE %r6, 0x12345678 

	lwz %r5, MGT5200_GPIOWIE(%r6)
	lis     %r7,0x8000				
	srw		%r7, %r7, %r4			/* shift mask bit to proper position */
	or      %r5,%r5,%r7             /* set bit to unmask */
	stw     %r5, MGT5200_GPIOWIE(%r6)             /* store new value */
	li      %r3,0
	blr
CALLOUT_END	interrupt_unmask_mgt5200_gpiow

/***************************************************************************
 * Callout : 	interrupt_mask_mgt5200_gpiow
 *
 * Description: Mask the given GPIO interrupt level
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_mask_mgt5200_gpiow, 0, patcher

/*
 * Mask the interrupt level that gets passed in r4. Clearing a bit in the 
 * WakeUP GPIO Individual Interrupt Enable Register masks the interrupt.
 */
	DEVBASE %r6, 0x12345678 
	
	lwz %r5, MGT5200_GPIOWIE(%r6)        
	lis     %r7,0x8000				
	srw		%r7, %r7, %r4			/* shift mask bit to proper position */
	andc    %r5,%r5,%r7             /* clear bit to mask */
	stw     %r5, MGT5200_GPIOWIE(%r6)             /* store new value */
	li      %r3,0
	blr
CALLOUT_END	interrupt_mask_mgt5200_gpiow


/***************************************************************************
 * Callout : 	interrupt_id_mgt5200_gpiow
 *
 * Description: Determine the GPIO interrupt level and mask it off.
 *
 * On Entry:	Nothing
 *
 * On Exit:		r14 = interrupt level
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_id_mgt5200_gpiow, 0, patcher

/*
 * Identify the interrupt level, mask it, and return the level in r14.
 */
 	DEVBASE %r6, 0x12345678 

	li		%r14, -1

    lwz     %r5,MGT5200_GPIOWSR(%r6)     

	lis		%r4, 0xff00
	and		%r5, %r5, %r4	/* clear bus error bits */

	cmplwi	%r5,0
	beq		1f		/* no interrupt bits set, spurious int */

	cntlzw  %r14,%r5                /* count leading zeros in r5, place resulting interrupt value in r14 */

  	lwz     %r4,MGT5200_GPIOWIE(%r6) 

	lis     %r5,0x8000
	srw     %r5,%r5,%r14            /* shift mask bit right to position of interrupt we wish to mask */
	stw		%r5, MGT5200_GPIOWSR(%r6)				/* write a 1 to clear the interrupt */
	andc    %r4,%r4,%r5             /* clear relevant bit to mask it */
	eieio
	stw     %r4, MGT5200_GPIOWIE(%r6)         
	sync
1:
CALLOUT_END	interrupt_id_mgt5200_gpiow

/***************************************************************************
 * Callout : 	interrupt_eoi_mgt5200_gpiow
 *
 * Description: Clear the interrupt, then unmask the level (it was masked in
 *				interrupt_id)
 *
 * On Entry:	r14 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_eoi_mgt5200_gpiow, 0, patcher

/*
 * clear the interrupt by writing a 1 to the appropriate bit in the status register, 
 * and unmask. r14 still holds the level.
 */
	DEVBASE %r6, 0x12345678 
	
    lwz     %r5,MGT5200_GPIOWSR(%r6)               

	lis		%r4, 0x8000
	srw		%r4, %r4, %r14				/* shift the bit to the proper position */
	stw		%r4, MGT5200_GPIOWSR(%r6)					/* write appropriate bit into r6. Don't read/modify/write, */
										/* or we might clear interrupts that haven't been serviced yet */

	cmplwi	%r18, 0
	bgt		1f

	lwz 	%r5, MGT5200_GPIOWIE(%r6)
	or      %r5,%r4,%r5             /* set bit to unmask */
	stw     %r5, MGT5200_GPIOWIE(%r6)             /* store new value */
1:
CALLOUT_END		interrupt_eoi_mgt5200_gpiow

/***************************************************************************
 *
 * Smartcomm Interrupt Callouts
 *
 ***************************************************************************/

/***************************************************************************
 * Callout : 	interrupt_unmask_mgt5200_sc
 *
 * Description: Unmask the given smartcomm interrupt level
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_unmask_mgt5200_sc, 0, patcher

/*
 * Unmask the interrupt level that gets passed in r4.
 */
 	DEVBASE %r6, 0x12345678 
 	
	cmplwi	%r4,24
	blt		1f						/* If it's less than 24, it's a task/EU int */

	/* Timer interrupt.  Need to enable int in the timer's control register */	
	li		%r7,7
	sub		%r4,%r7,%r4		/* 7 - r4 = timer number 1:7 */
	li		%r7,4
	slw		%r4,%r4,%r7		/* Get the offset of the individual timer control register */
	addi	%r4,%r4,4
	lis		%r5,MGT5200_SCTMR@ha
	la		%r5,MGT5200_SCTMR@l(%r5)
	add		%r5,%r5,%r4
	add		%r5,%r5,%r6
	lwz		%r7,0(%r5)		/* Load the timer control register */
	ori		%r7,%r7,0x0010			/* Set the IE bit to unmask the individual timer */
	eieio
	stw		%r7,0(%r5)	/* Store the timer control value back to the register */
	sync
	b		2f
	
/* Task or EU interrupt. Setting a bit in the Smartcomm Interrupt Mask
 * Register masks the interrupt, clearing the bit unmasks.
 */
1:
	lwz %r5, MGT5200_SCIMR(%r6)                 /* load contents of Smartcomm Interrupt Mask Register into r5 */
	lis     %r7,0x0080				
	srw		%r7, %r7, %r4			/* shift mask bit to proper position */
	andc    %r5,%r5,%r7             /* unmask bit */
	stw     %r5, MGT5200_SCIMR(%r6)             /* store new value */
	li      %r3,0
2:	
	blr
CALLOUT_END	interrupt_unmask_mgt5200_sc

/***************************************************************************
 * Callout : 	interrupt_mask_mgt5200_sc
 *
 * Description: Mask the given smartcomm interrupt level
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_mask_mgt5200_sc, 0, patcher

/*
 * Mask the interrupt level that gets passed in r4.
 */
 	DEVBASE %r6, 0x12345678 
 	
	cmplwi	%r4,24
	blt		1f						/* If it's less than 24, it's a task/EU int */

	/* Timer interrupt.  Need to disable int in the timer's control register */	
	li		%r7,7
	sub		%r4,%r7,%r4		/* 7 - r4 = timer number 1:7 */
	li		%r7,4
	slw		%r4,%r4,%r7		/* Get the offset of the individual timer control register */
	addi	%r4,%r4,4
	lis		%r5,MGT5200_SCTMR@ha
	la		%r5,MGT5200_SCTMR@l(%r5)
	add		%r5,%r5,%r4
	add		%r5,%r5,%r6
	lwz		%r7,0(%r5)		/* Load the timer control register */
	andi.	%r7,%r7,0xffef			/* Clear the IE bit to mask the individual timer */
	eieio
	stw		%r7,0(%r5)	/* Store the timer control value back to the register */
	sync
	b		2f
	
/* Task or EU interrupt. Setting a bit in the Smartcomm Interrupt Mask
 * Register masks the interrupt, clearing the bit unmasks.
 */
1:
	lwz %r5, MGT5200_SCIMR(%r6)                 /* load contents of Smartcomm Interrupt Mask Register into r5 */
	lis     %r7,0x0080				
	srw		%r7, %r7, %r4			/* shift mask bit to proper position */
	or      %r5,%r5,%r7             /* mask bit */
	stw     %r5, MGT5200_SCIMR(%r6)             /* store new value */
	li      %r3,0
2:
	blr
CALLOUT_END	interrupt_mask_mgt5200_sc


/***************************************************************************
 * Callout : 	interrupt_id_mgt5200_sc
 *
 * Description: Determine the smartcomm interrupt level and mask it off.
 *
 * On Entry:	Nothing
 *
 * On Exit:		r14 = smartcomm interrupt level
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_id_mgt5200_sc, 0, patcher

/*
 * Identify the interrupt level, mask it, and return the level in r14.
 */
 	DEVBASE %r6, 0x12345678 
 
 	lwz		%r5,MGT5200_SCTSR(%r6)
 	
 	andis.	%r5,%r5,0x0100	/* Check SC_int */
 	bne		1f
 	
 	lwz		%r5,MGT5200_SCTSR(%r6)
 	andis.	%r5,%r5,0x00fe	/* Check timer interrupt status */
	cntlzw  %r14,%r5        /* count leading zeros in r5, place resulting interrupt value in r14 */
	subi	%r4,%r14,8		/* account for 8 leading zero bits before int status field */
	addi	%r14,%r4,24		/* Add 24 to place timer int vectors after EU and Task ints */	
	
	/* r4 contains relative timer interrupt vector number (7:1) */
	li		%r7,7
	sub		%r4,%r6,%r4		/* 7 - r4 = timer number 1:7 */
	li		%r7,4
	slw		%r4,%r4,%r7		/* Get the offset of the individual timer control register */
	addi	%r4,%r4,4
	lis		%r5,MGT5200_SCTMR@ha
	la		%r5,MGT5200_SCTMR@l(%r5)
	add		%r5,%r5,%r4
	add		%r5,%r5,%r6
	lwz		%r7,0(%r5)		/* Load the timer control register */
	andi.	%r7,%r7,0xffef			/* Clear the IE bit to mask the individual timer */
	eieio
	stw		%r7,0(%r5)	/* Store the timer control value back to the register */
	sync
	b		2f
 	
1:
    lwz     %r5,MGT5200_SCIPR(%r6)                  /* put Smartcomm Interrupt Pending Register in r5 */

    lwz     %r4,MGT5200_SCIMR(%r6)                  /* put Smartcomm Interrupt Mask Register in r4 */

	andc	%r5,%r5,%r4				/* consider only unmasked pending interrupts */
	cntlzw  %r14,%r5                /* count leading zeros in r5, place resulting interrupt value in r14 */
	subi	%r14, %r14, 8			/* account for 8 reserved bits at beginning of SCIPR */

	lis     %r5,0x0080
	srw     %r5,%r5,%r14            /* shift mask bit right to position of interrupt we wish to mask */
	or      %r4,%r4,%r5             /* set relevant bit to mask it */
	eieio
	stw     %r4, MGT5200_SCIMR(%r6)             /* load new enable mask into SCIMR */
	sync
2:
CALLOUT_END	interrupt_id_mgt5200_sc

/***************************************************************************
 * Callout : 	interrupt_eoi_mgt5200_sc
 *
 * Description: Clear the interrupt, then unmask the level (it was masked in
 *				interrupt_id)
 *
 * On Entry:	r14 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_eoi_mgt5200_sc, 0, patcher

/*
 * Clear and unmask the interrupt level that gets passed in r4.
 */
	DEVBASE %r6, 0x12345678 
	
 	cmplwi	%r14,24
	blt		1f						/* If it's less than 24, it's a task/EU int */
	
	/* 
	 * For timer ints, we just enable the interrupt again.  User ISR will have
	 * to be responsible for clearing the interrupt condition by resetting
	 * the timer.
	 */

	/* Timer interrupt.  Need to enable int in the timer's control register */	
	li		%r7,7
	sub		%r4,%r7,%r14		/* 7 - r14 = timer number 1:7 */
	li		%r7,4
	slw		%r4,%r4,%r7		/* Get the offset of the individual timer control register */
	addi	%r4,%r4,4
	lis		%r5,MGT5200_SCTMR@ha
	la		%r5,MGT5200_SCTMR@l(%r5)
	add		%r5,%r5,%r4
	add      %r5,%r5,%r6
	lwz		%r7,0(%r5)		/* Load the timer control register */
	ori		%r7,%r7,0x0010			/* Set the IE bit to unmask the individual timer */
	eieio
	stw		%r7,0(%r5)	/* Store the timer control value back to the register */
	sync
	b		2f
	
1:

/*
 * Task or EU interrupt.
 */
	cmplwi	%r18, 0
	bgt		2f

    lwz     %r5,MGT5200_SCIMR(%r6)                  /* put Smartcomm Interrupt Mask Register in r5 */

	lis		%r4, 0x0080
	srw		%r4, %r4, %r14				/* shift the bit to the proper position */
	andc	%r5, %r5, %r4				/* unmask by clearing the appropriate bit */
    stw     %r5, MGT5200_SCIMR(%r6)
2:	
CALLOUT_END		interrupt_eoi_mgt5200_sc