callout_interrupt_mgt5200.s

qnx powerpc MPC8245的 BSP源文件

 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_unmask_mgt5200_per_hi, 0, patcher

/*
 * Setting a bit in the Peripheral Interrupt Mask Register masks the interrupt
 * Clearing the bit unmasks.
 */
 	DEVBASE %r6, 0x12345678
 	
	lwz %r5, MGT5200_PIMR(%r6)                 /* load contents of Peripheral Interrupt Mask Register into r5 */
	lis     %r8,0x8000				
	srw		%r8, %r8, %r4			/* shift mask bit to proper position */
	andc    %r5,%r5,%r8             /* unmask bit */
	stw     %r5, MGT5200_PIMR(%r6)             /* store new value */
	li      %r3,0
	blr
CALLOUT_END	interrupt_unmask_mgt5200_per_hi

/***************************************************************************
 * Callout : 	interrupt_mask_mgt5200_per_hi
 *
 * Description: Mask the given peripheral interrupt level for HI ints
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_mask_mgt5200_per_hi, 0, patcher

/*
 * Setting a bit in the Peripheral Interrupt Mask Register masks the interrupt
 * Clearing the bit unmasks.
 */
 	DEVBASE %r6, 0x12345678
 	
	lwz %r5, MGT5200_PIMR(%r6)                 /* load contents of Peripheral Interrupt Mask Register into r5 */
	lis     %r8,0x8000				
	srw		%r8, %r8, %r4			/* shift mask bit to proper position */
	or      %r5,%r5,%r8             /* mask bit */
	stw     %r5, MGT5200_PIMR(%r6)             /* store new value */
	li      %r3,0
	blr
CALLOUT_END	interrupt_mask_mgt5200_per_hi


/***************************************************************************
 * Callout : 	interrupt_id_mgt5200_per_hi
 *
 * Description: Determine the HI peripheral interrupt level and mask it off.
 *
 * On Entry:	Nothing
 *
 * On Exit:		r14 = peripheral interrupt level
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_id_mgt5200_per_hi, 0, patcher

/*
 *  Make a mask out of the bits in each of the three HLSR registers that
 *  define whether a peripheral interrupt is HI or LO, and mask off all
 *  that are programmed LO 
 */
	DEVBASE %r6, 0x12345678

	li      %r14, -1

	lwz		%r5,MGT5200_ALL_STAT_ENC(%r6)

	lis     %r4, 0x2000     /* Peripheral Status flag */
	and     %r4, %r4, %r5   /* clear all bits except status */
	cmplwi  %r4,0
	beq     1f              /* No peripheral interrupt, return -1 */

	andi.   %r4,%r5,0x300   /* check if HI_int is the source */
	cmplwi  %r4,0x200
	bne     1f              /* not a HI int */

	andis.  %r5,%r5,0x1f00  /* Mask and shift PerStat field */
	li      %r4,24
	srw     %r14,%r5,%r4

	lwz     %r4,MGT5200_PIMR(%r6)   /* put Peripheral Interrupt Mask Register in r4 */

	ori     %r4, %r4, 0xff          /* set reserved bits to make them appear masked */

	lis     %r5,0x8000
	srw     %r5,%r5,%r14            /* shift mask bit right to position of interrupt we wish to mask */
	or      %r4,%r4,%r5             /* set relevant bit to mask it */
	eieio
	stw     %r4, MGT5200_PIMR(%r6)             /* load new enable mask into PIMR */
	sync
1:	
CALLOUT_END	interrupt_id_mgt5200_per_hi

/***************************************************************************
 * Callout : 	interrupt_eoi_mgt5200_per_hi
 *
 * Description: Clear the interrupt, then unmask the level (it was masked in
 *				interrupt_id)
 *
 * On Entry:	r14 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_eoi_mgt5200_per_hi, 0, patcher

/*
 * All peripheral interrupts are level triggered, active high. When the ISR
 * clears the interrupt at the source, the level goes low again, and the
 * updated status is reflected in the PISR. So, it's not necessary to clear
 * the interrupt here, we just have to unmask it.
 */
	DEVBASE %r6, 0x12345678 
	
	cmplwi	%r18, 0
	bgt		1f

    lwz     %r5,MGT5200_PIMR(%r6)                  /* put Peripheral Interrupt Mask Register in r5 */

	lis		%r4, 0x8000
	srw		%r4, %r4, %r14				/* shift the bit to the proper position */
	andc	%r5, %r5, %r4				/* unmask by clearing the appropriate bit */
    stw     %r5, MGT5200_PIMR(%r6)
1:	
CALLOUT_END		interrupt_eoi_mgt5200_per_hi

/***************************************************************************
 * Callout : 	interrupt_unmask_mgt5200_per_lo
 *
 * Description: Unmask the given peripheral interrupt level, for LO interrupts
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_unmask_mgt5200_per_lo, 0, patcher

/*
 * Setting a bit in the Peripheral Interrupt Mask Register masks the interrupt
 * Clearing the bit unmasks.
 */
 	DEVBASE %r6, 0x12345678 
 	
	lwz %r5, MGT5200_PIMR(%r6)                 /* load contents of Peripheral Interrupt Mask Register into r5 */
	lis     %r7,0x8000				
	srw		%r7, %r7, %r4			/* shift mask bit to proper position */
	andc    %r5,%r5,%r7             /* unmask bit */
	stw     %r5, MGT5200_PIMR(%r6)             /* store new value */
	li      %r3,0
	blr
CALLOUT_END	interrupt_unmask_mgt5200_per_lo

/***************************************************************************
 * Callout : 	interrupt_mask_mgt5200_per_lo
 *
 * Description: Mask the given peripheral interrupt level
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_mask_mgt5200_per_lo, 0, patcher

/*
 * Setting a bit in the Peripheral Interrupt Mask Register masks the interrupt
 * Clearing the bit unmasks.
 */
 	DEVBASE %r6, 0x12345678
 	
	lwz %r5, MGT5200_PIMR(%r6)                 /* load contents of Peripheral Interrupt Mask Register into r5 */
	lis     %r7,0x8000				
	srw		%r7, %r7, %r4			/* shift mask bit to proper position */
	or      %r5,%r5,%r7             /* mask bit */
	stw     %r5, MGT5200_PIMR(%r6)             /* store new value */
	li      %r3,0
	blr
CALLOUT_END	interrupt_mask_mgt5200_per_lo


/***************************************************************************
 * Callout : 	interrupt_id_mgt5200_per_lo
 *
 * Description: Determine the peripheral interrupt level and mask it off.
 *
 * On Entry:	Nothing
 *
 * On Exit:		r14 = peripheral interrupt level
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_id_mgt5200_per_lo, 0, patcher

/*
 *  Make a mask out of the bits in each of the three HLSR registers that
 *  defines whether a peripheral interrupt is HI or LO, and mask off all
 *  that are programmed HI 
 */
	DEVBASE %r6, 0x12345678 

	li      %r14, -1

	lwz		%r5,MGT5200_ALL_STAT_ENC(%r6)

	lis     %r4, 0x2000     /* Peripheral Status flag */
	and     %r4, %r4, %r5   /* clear all bits except status */
	cmplwi  %r4,0
	beq     1f              /* No peripheral interrupt, return -1 */

	andi.   %r4,%r5,0x300   /* check if HI_int is the source */
	cmplwi  %r4,0x200
	beq     1f              /* this is a HI int */

	andis.  %r5,%r5,0x1f00  /* Mask and shift PerStat field */
	li      %r4,24
	srw     %r14,%r5,%r4

	lwz     %r4,MGT5200_PIMR(%r6)   /* put Peripheral Interrupt Mask Register in r4 */

	ori     %r4, %r4, 0xff          /* set reserved bits to make them appear masked */

	lis     %r5,0x8000
	srw     %r5,%r5,%r14            /* shift mask bit right to position of interrupt we wish to mask */
	or      %r4,%r4,%r5             /* set relevant bit to mask it */
	eieio
	stw     %r4, MGT5200_PIMR(%r6)             /* load new enable mask into PIMR */
	sync
1:	
CALLOUT_END	interrupt_id_mgt5200_per_lo

/***************************************************************************
 * Callout : 	interrupt_eoi_mgt5200_per_lo
 *
 * Description: Clear the interrupt, then unmask the level (it was masked in
 *				interrupt_id)
 *
 * On Entry:	r14 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_eoi_mgt5200_per_lo, 0, patcher

/*
 * All peripheral interrupts are level triggered, active high. When the ISR
 * clears the interrupt at the source, the level goes low again, and the
 * updated status is reflected in the PISR. So, it's not necessary to clear
 * the interrupt here, we just have to unmask it.
 */
 	DEVBASE %r6, 0x12345678 

	cmplwi	%r18, 0
	bgt		1f

    lwz     %r5,MGT5200_PIMR(%r6)                  /* put Peripheral Interrupt Mask Register in r5 */

	lis		%r4, 0x8000
	srw		%r4, %r4, %r14				/* shift the bit to the proper position */
	andc	%r5, %r5, %r4				/* unmask by clearing the appropriate bit */
    stw     %r5, MGT5200_PIMR(%r6)
1:	
CALLOUT_END		interrupt_eoi_mgt5200_per_lo


/*************************************************************************************
 *
 * Simple GPIO callouts
 *
 *************************************************************************************/
/***************************************************************************
 * Callout : 	interrupt_unmask_mgt5200_gpio
 *
 * Description: Unmask the given GPIO interrupt level
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_unmask_mgt5200_gpio, 0, patcher

/*
 * Unmask the interrupt level that gets passed in r4. Setting a bit 
 * in the Wakeup GPIO Individual Interrupt Enable Register unmasks the interrupt.
 */
 	DEVBASE %r6, 0x12345678 
 	
	lwz     %r5, MGT5200_GPIOSIIE(%r6)
	lis     %r7,0x8000				
	srw	    %r7, %r7, %r4			/* shift mask bit to proper position */
	or      %r5,%r5,%r7             /* set bit to unmask */
	stw     %r5, MGT5200_GPIOSIIE(%r6)             /* store new value */
	li      %r3,0
	sync
	blr
CALLOUT_END	interrupt_unmask_mgt5200_gpio

/***************************************************************************
 * Callout : 	interrupt_mask_mgt5200_gpio
 *
 * Description: Mask the given GPIO interrupt level
 *
 * On Entry:	r4 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_mask_mgt5200_gpio, 0, patcher

/*
 * Mask the interrupt level that gets passed in r4. Clearing a bit in the 
 * WakeUP GPIO Individual Interrupt Enable Register masks the interrupt.
 */
	DEVBASE %r6, 0x12345678 
	
	lwz %r5, MGT5200_GPIOSIIE(%r6)        
	lis     %r7,0x8000				
	srw		%r7, %r7, %r4			/* shift mask bit to proper position */
	andc    %r5,%r5,%r7             /* clear bit to mask */
	stw     %r5, MGT5200_GPIOSIIE(%r6)             /* store new value */
	li      %r3,0
	blr
CALLOUT_END	interrupt_mask_mgt5200_gpio


/***************************************************************************
 * Callout : 	interrupt_id_mgt5200_gpio
 *
 * Description: Determine the GPIO interrupt level and mask it off.
 *
 * On Entry:	Nothing
 *
 * On Exit:		r14 = interrupt level
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_id_mgt5200_gpio, 0, patcher

/*
 * Identify the interrupt level, mask it, and return the level in r14.
 */
 	DEVBASE %r6, 0x12345678 

	li		%r14, -1

    lwz     %r5,MGT5200_GPIOSSR(%r6)     

	lis		%r4, 0xff00
	and		%r5, %r5, %r4	/* clear input value bits */

	cmplwi	%r5,0
	beq		1f		        /* no interrupt bits set, spurious int */

	cntlzw  %r14,%r5      /* count leading zeros in r5, place resulting interrupt value in r14 */

    /* Masking the corresponding GPIO bit in GPIO IE Register */
    lwz     %r4,MGT5200_GPIOSIIE(%r6) 

	lis     %r5,0x8000
	srw     %r5,%r5,%r14            /* shift mask bit right to position of interrupt we wish to mask */
	stw		%r5, MGT5200_GPIOSSR(%r6)				/* clear the interrupt by writing a 1 to the bit */
	andc    %r4,%r4,%r5             /* clear relevant bit to mask it */
	eieio
	stw     %r4, MGT5200_GPIOSIIE(%r6)         
	sync
1:
CALLOUT_END	interrupt_id_mgt5200_gpio

/***************************************************************************
 * Callout : 	interrupt_eoi_mgt5200_gpio
 *
 * Description: Clear the interrupt, then unmask the level (it was masked in
 *				interrupt_id)
 *
 * On Entry:	r14 = interrupt level
 *
 * On Exit:		Nothing
 *
 * Notes:
 *
 **************************************************************************/
CALLOUT_START	interrupt_eoi_mgt5200_gpio, 0, patcher