callout_cache_ppc700smp.s

qnx powerpc MPC8245的 BSP源文件

#  
# Copyright 2007, QNX Software Systems. 
#  
# Licensed under the Apache License, Version 2.0 (the "License"). You 
# may not reproduce, modify or distribute this software except in 
# compliance with the License. You may obtain a copy of the License 
# at: http://www.apache.org/licenses/LICENSE-2.0 
#  
# Unless required by applicable law or agreed to in writing, software 
# distributed under the License is distributed on an "AS IS" basis, 
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
# 
# This file may contain contributions from others, either as 
# contributors under the License or as licensors under other terms.  
# Please review this entire file for other proprietary rights or license 
# notices, as well as the QNX Development Suite License Guide at 
# http://licensing.qnx.com/license-guide/ for other information.
# 
# This is a kernel hardware callout.
# This code MUST be position independant.
#

	.include "callout.ah"

#
# unsigned control(	paddr32_t base,
#					unsigned num_lines,
#					int flags,
#					struct cacheattr_entry *cache,
#					volatile struct syspage_entry * )


#
# Perform the cache controller operations indicated by 'flags' 
# (MS_* bits passed to the msync() function).
#
CALLOUT_START	cache_ippc_700smp, 0, 0
		# For 750 SMP, we just flush the whole icache -- caches
		# are not coherent and thsi simplifies the job of cache flushing
		mfspr   %r3,PPC700_SPR_HID0
		ori             %r5,%r3,0x800
		mtspr   PPC700_SPR_HID0,%r5
		isync
		mtspr   PPC700_SPR_HID0,%r3
		sync
		isync
		mr	%r3,%r4
		blr
CALLOUT_END		cache_ippc_700smp

CALLOUT_START	cache_dppc_700smp, 0, 0
		# Don't try to do all lines (preemption)
		lwz		%r9,CA_LINE_SIZE(%r6)
		cmpwi	%r4,64
		ble		1f
		li		%r4,64
1:
		ori		%r8,%r3,0
		bittst	%r0,%r5,(MS_SYNC | MS_ASYNC)
		beq		1f
		mtctr	%r4
2:
		# We first touch the line to make sure this CPU has ownership, then
		# the cache flush will work. If we don't do this, we end up with stale
		# data in the other processor's cache due to the fact the 750 does not
		# snoop cache operations.
		lwz		%r11,0(%r8)
		dcbst	0,%r8			# Flush from data cache	
		add		%r8,%r8,%r9
		bdnz+	2b
1:
		bittst	%r0,%r5,MS_INVALIDATE
		beq		1f
		mtctr	%r4
2:
		# We first touch the line to make sure this CPU has ownership, then
		# the cache flush will work. If we don't do this, we end up with stale
		# data in the other processor's cache due to the fact the 750 does not
		# snoop cache operations.
		lwz		%r11,0(%r3)
		dcbi	0,%r3			# invalidate from data cache
		add		%r3,%r3,%r9
		bdnz+	2b
1:
		ori		%r3,%r4,0		# we did all requested lines
		sync
		blr
CALLOUT_END		cache_dppc_700smp