gt64260_init_raminfo.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */


/*
 * init_raminfo.c
 *	Tell syspage about our RAM configuration
 */
#include "startup.h"
#include "gt64260.h"

#define SCS_0_LOW						0x0008
#define SCS_0_HIGH						0x0010
#define SCS_1_LOW						0x0208
#define SCS_1_HIGH						0x0210
#define SCS_2_LOW						0x0018
#define SCS_2_HIGH						0x0020
#define SCS_3_LOW						0x0218
#define SCS_3_HIGH						0x0220

void gt64260_init_raminfo(unsigned long gt64260_base) {
	unsigned	size = 0, base, high;
	uintptr_t	gtbase;

	gtbase = startup_io_map(0x10000,gt64260_base);

	// Check the individual banks in the SDRAM controller

	// SCS0
	base = 0xffff & inle32(gtbase+SCS_0_LOW);
	high = 0xfff & inle32(gtbase+SCS_0_HIGH);
	if (base != 0xffff) 
		size += (high + 1) - base;
	// SCS1
	base = 0xffff & inle32(gtbase+SCS_1_LOW);
	high = 0xfff & inle32(gtbase+SCS_1_HIGH);
	if (base != 0xffff) 
		size += (high + 1) - base;
	// SCS2
	base = 0xffff & inle32(gtbase+SCS_2_LOW);
	high = 0xfff & inle32(gtbase+SCS_2_HIGH);
	if (base != 0xffff) 
		size += (high + 1) - base;
	// SCS3
	base = 0xffff & inle32(gtbase+SCS_3_LOW);
	high = 0xfff & inle32(gtbase+SCS_3_HIGH);
	if (base != 0xffff) 
		size += (high + 1) - base;

	add_ram(0x0, size << 20);

    // set up PCI snoop control regs - CPU snoop regs are set up in IPL

    size -= 1;
    out32(gtbase + PCI0_SNOOP_CONTROL0_BASE_LOW,ENDIAN_LE32(0x00002000));
    out32(gtbase + PCI0_SNOOP_CONTROL0_BASE_HI,ENDIAN_LE32(0x00000000));
    out32(gtbase + PCI0_SNOOP_CONTROL0_TOP,ENDIAN_LE32(size));

    out32(gtbase + PCI1_SNOOP_CONTROL0_BASE_LOW,ENDIAN_LE32(0x00002000));
    out32(gtbase + PCI1_SNOOP_CONTROL0_BASE_HI,ENDIAN_LE32(0x00000000));
    out32(gtbase + PCI1_SNOOP_CONTROL0_TOP,ENDIAN_LE32(size));

	startup_io_unmap(gtbase);
}