ppc440gp_set_clock_freqs.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */



/*
 * ppc440gp_set_clock_freqs.c
 * Set the cpu_freq, cycles_freq, and timer_freq variables, based on
 * the main system clock
 *
 */

#include "startup.h"
#include <ppc/440cpu.h>

extern unsigned long ppc4xx_opbclock;

void
ppc440gp_set_clock_freqs(unsigned sys_clk) {
	unsigned	sys0;
	unsigned	core_clock;
	unsigned	fbdv;
	unsigned	fwdva;
	unsigned	fwdvb;
	unsigned	epdv;
	unsigned	opdv;
	unsigned	m, vco_clk, plb_clk;

	sys0 = get_dcr(PPC440_DCR_CPC0_SYS0);

	fbdv = (sys0 & PPC440GP_CPC0_SYS0_FBDV_MASK) >> PPC440GP_CPC0_SYS0_FBDV_SHIFT;
	if (fbdv == 0) fbdv = 16;
	epdv = ((sys0 & PPC440GP_CPC0_SYS0_EPDV_MASK) >> PPC440GP_CPC0_SYS0_EPDV_SHIFT) + 1;
	opdv = ((sys0 & PPC440GP_CPC0_SYS0_OPDV_MASK) >> PPC440GP_CPC0_SYS0_OPDV_SHIFT) + 1;
	fwdva = 8 - ((sys0 & PPC440GP_CPC0_SYS0_FWDVA_MASK) >> PPC440GP_CPC0_SYS0_FWDVA_SHIFT);
	fwdvb = 8 - ((sys0 & PPC440GP_CPC0_SYS0_FWDVB_MASK) >> PPC440GP_CPC0_SYS0_FWDVB_SHIFT);

	/* Calculate 'M' based on feedback source */
	if(sys0 & PPC440GP_CPC0_SYS0_BYPASS)
		m = epdv * opdv * fwdvb;
	else
		m = fbdv * fwdva;

	vco_clk = (m * sys_clk) + (m >> 1);
	plb_clk = vco_clk / fwdvb;
	ppc4xx_opbclock = plb_clk / opdv;

	core_clock = vco_clk / fwdva;

	if (timer_freq == 0) timer_freq = core_clock;
	if (cycles_freq == 0) cycles_freq = core_clock;

	if (cpu_freq == 0) {
		if (sys0 & PPC440GP_CPC0_SYS0_EXTSL) {
			// per clk
			cpu_freq = ((uint64_t)core_clock
					  * (uint64_t)epdv
					  * (uint64_t)opdv
					  * (uint64_t)fwdvb) / fwdva;
		}
		else {
			// cpu clk
			cpu_freq = core_clock;
		}
	}
}