ppcv_cpuconfig_e500.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */

#include "startup.h"
#include <ppc/e500cpu.h>

void
ppcv_cpuconfig1_e500(int cpu) {
	unsigned	npids;
	unsigned	hid;
	unsigned	l1c;

	//Init the HID registers
	hid = get_spr(PPCE500_SPR_HID0) & PPCE500_HID0_SEL_TBCLK;
	set_spr(PPCE500_SPR_HID0, hid 
				| PPCE500_HID0_EMCP
				| PPCE500_HID0_DOZE
				| PPCE500_HID0_TBEN);
	hid = get_spr(PPCE500_SPR_HID1) | (PPCE500_HID1_MSHARS|PPCE500_HID1_SSHAR);
	set_spr(PPCE500_SPR_HID1, hid);

	//Init the L1 caches
	l1c = get_spr(PPCE500_SPR_L1CSR0);
	if(!(l1c & PPCE500_L1CSR0_CE)) {
		// flash invalidate data cache
		set_spr(PPCE500_SPR_L1CSR0, l1c | PPCE500_L1CSR0_CFI);
		do {
		} while(get_spr(PPCE500_SPR_L1CSR0) & PPCE500_L1CSR0_CFI);
		set_spr(PPCE500_SPR_L1CSR0, l1c | PPCE500_L1CSR0_CE);
	}
	l1c = get_spr(PPCE500_SPR_L1CSR1);
	if(!(l1c & PPCE500_L1CSR1_ICE)) {
		// flash invalidate instruction cache
		set_spr(PPCE500_SPR_L1CSR1, l1c | PPCE500_L1CSR1_ICFI);
		do {
		} while(get_spr(PPCE500_SPR_L1CSR1) & PPCE500_L1CSR1_ICFI);
		set_spr(PPCE500_SPR_L1CSR1, l1c | PPCE500_L1CSR1_ICE);
	}

	set_spr(PPCBKEM_SPR_MAS4, PPCBKEM_MAS4_SHAREND
			| (PPCBKE_TLB_SIZE_4K << PPCBKEM_MAS4_TSIZED_SHIFT)
			| PPCBKEM_MAS4_MD);
	npids = (get_spr(PPCBKEM_SPR_MMUCFG) & PPCBKEM_MMUCFG_NPIDS_MASK) >> PPCBKEM_MMUCFG_NPIDS_SHIFT;
	switch(npids) {
	default:
	case 3:
		set_spr(PPCBKEM_SPR_PID2, 0);
		// fall through
	case 2:
		set_spr(PPCBKEM_SPR_PID1, 0);
		// fall through
	}
	set_spr(PPCE500_SPR_BUCSR, PPCE500_BUCSR_BPEN);

	ppcv_cpuconfig1_booke(cpu);
}

void
ppcv_cpuconfig2_e500(int cpu) {
	ppcv_cpuconfig2_booke(cpu);
	//NYI: Anything else?
}