callout_sendipi_mv64360.s

qnx powerpc MPC8245的 BSP源文件

#  
# Copyright 2007, QNX Software Systems. 
#  
# Licensed under the Apache License, Version 2.0 (the "License"). You 
# may not reproduce, modify or distribute this software except in 
# compliance with the License. You may obtain a copy of the License 
# at: http://www.apache.org/licenses/LICENSE-2.0 
#  
# Unless required by applicable law or agreed to in writing, software 
# distributed under the License is distributed on an "AS IS" basis, 
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
# 
# This file may contain contributions from others, either as 
# contributors under the License or as licensors under other terms.  
# Please review this entire file for other proprietary rights or license 
# notices, as well as the QNX Development Suite License Guide at 
# http://licensing.qnx.com/license-guide/ for other information.
# 
# An entry point for a hardware kernel callout.
# It may be called by an interrupt handler.
# This code MUST be position independant.
#

	.include "callout.ah"
	
	.extern	mv64360_base

# R3: syspage paddr
# R4: syspage vaddr
# R5: rtn dst offset
# R6: r/w offset
# R7: patch data
# R8: rtn src

patcher:
	stwu	%r1,-32(%r1)
	mflr	%r0
	stw		%r31,28(%r1)
	stw		%r0,36(%r1)
	
	add		%r31,%r3,%r5
	
   	loada	%r4,mv64360_base
	loadi	%r3,0x30000
	bl		callout_io_map_indirect

	lhz		%r4,6(%r31)
	lhz		%r5,2(%r31)
	slwi	%r5,%r5,16
	or		%r4,%r4,%r5
	add		%r3,%r3,%r4
	sth		%r3,6(%r31)
	srwi	%r3,%r3,16
	sth		%r3,2(%r31)
	
	lwz		%r0,36(%r1)
	mtlr	%r0
	lwz		%r31,28(%r1)
	addi	%r1,%r1,32
	blr
	
.macro DEVBASE reg,dev_reg_off
	# the instruction immediate values are patched by the above routine
	lis		&reg,(&dev_reg_off) >> 16
	ori		&reg,&reg,(&dev_reg_off) & 0xffff
.endm

.set 	CPU0_DOORBELL,	0x214
.set	CPU1_DOORBELL,	0x224
		
CALLOUT_START	sendipi_mv64360, 0, patcher

#
# Send an IPI (new style).
#
#
# %r3: syspage ptr
# %r4: cpunum to send IPI to
# %r5: ipi code (command to send)
# %r6: &ipicmds
#
	DEVBASE	%r7,0

	# Disable interrupts
	loadi	%r9,PPC_MSR_EE
	mfmsr	%r8
	andc	%r9,%r8,%r9
	mtmsr	%r9

	# set IPI command
2:
	lwarx	%r3,%r0,%r6
	or		%r3,%r3,%r5
	stwcx.	%r3,%r0,%r6
	bne-	2b

	# determine which CPU is receiving the interrupt
	cmpwi	%r4,1
	beq		1f
	loadi	%r9,CPU0_DOORBELL
	b		2f
1:
	loadi	%r9,CPU1_DOORBELL
2:
	lbzx	%r6,%r7,%r9
	ori		%r11,%r6,0x01
	stbx	%r11,%r7,%r9

	#re-enable interrupts
	mtmsr	%r8
	blr
CALLOUT_END		sendipi_mv64360