📄 400intr.h
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/* * $QNXLicenseC: * Copyright 2007, QNX Software Systems. * * Licensed under the Apache License, Version 2.0 (the "License"). You * may not reproduce, modify or distribute this software except in * compliance with the License. You may obtain a copy of the License * at: http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" basis, * WITHOUT WARRANTIES OF ANY KIND, either express or implied. * * This file may contain contributions from others, either as * contributors under the License or as licensors under other terms. * Please review this entire file for other proprietary rights or license * notices, as well as the QNX Development Suite License Guide at * http://licensing.qnx.com/license-guide/ for other information. * $ *//* * PPC400 interrupt number definitions * * * */#ifndef __PPC_400INTR_H_INCLUDED#define __PPC_400INTR_H_INCLUDED#include <ppc/intr.h>/* external class */#define PPC403_INTR_CI (_NTO_INTR_CLASS_EXTERNAL + 0)#define PPC403_INTR_SRI (_NTO_INTR_CLASS_EXTERNAL + 4)#define PPC403_INTR_STI (_NTO_INTR_CLASS_EXTERNAL + 5)#define PPC403_INTR_JRI (_NTO_INTR_CLASS_EXTERNAL + 6)#define PPC403_INTR_JTI (_NTO_INTR_CLASS_EXTERNAL + 7)#define PPC403_INTR_D0I (_NTO_INTR_CLASS_EXTERNAL + 8)#define PPC403_INTR_D1I (_NTO_INTR_CLASS_EXTERNAL + 9)#define PPC403_INTR_D2I (_NTO_INTR_CLASS_EXTERNAL + 10)#define PPC403_INTR_D3I (_NTO_INTR_CLASS_EXTERNAL + 11)#define PPC403_INTR_E0I (_NTO_INTR_CLASS_EXTERNAL + 27)#define PPC403_INTR_E1I (_NTO_INTR_CLASS_EXTERNAL + 28)#define PPC403_INTR_E2I (_NTO_INTR_CLASS_EXTERNAL + 29)#define PPC403_INTR_E3I (_NTO_INTR_CLASS_EXTERNAL + 30)#define PPC403_INTR_E4I (_NTO_INTR_CLASS_EXTERNAL + 31)#define PPC405_INTR_U0I (_NTO_INTR_CLASS_EXTERNAL + 0)#define PPC405_INTR_U1I (_NTO_INTR_CLASS_EXTERNAL + 1)#define PPC405_INTR_IICI (_NTO_INTR_CLASS_EXTERNAL + 2)#define PPC405_INTR_EMII (_NTO_INTR_CLASS_EXTERNAL + 3)#define PPC405_INTR_PCII (_NTO_INTR_CLASS_EXTERNAL + 4)#define PPC405_INTR_D0I (_NTO_INTR_CLASS_EXTERNAL + 5)#define PPC405_INTR_D1I (_NTO_INTR_CLASS_EXTERNAL + 6)#define PPC405_INTR_D2I (_NTO_INTR_CLASS_EXTERNAL + 7)#define PPC405_INTR_D3I (_NTO_INTR_CLASS_EXTERNAL + 8)#define PPC405_INTR_EWI (_NTO_INTR_CLASS_EXTERNAL + 9)#define PPC405_INTR_MSI (_NTO_INTR_CLASS_EXTERNAL + 10)#define PPC405_INTR_MTEI (_NTO_INTR_CLASS_EXTERNAL + 11)#define PPC405_INTR_MREI (_NTO_INTR_CLASS_EXTERNAL + 12)#define PPC405_INTR_MTDI (_NTO_INTR_CLASS_EXTERNAL + 13)#define PPC405_INTR_MRDI (_NTO_INTR_CLASS_EXTERNAL + 14)#define PPC405_INTR_EI (_NTO_INTR_CLASS_EXTERNAL + 15)#define PPC405_INTR_EPSI (_NTO_INTR_CLASS_EXTERNAL + 16)#define PPC405_INTR_ECI (_NTO_INTR_CLASS_EXTERNAL + 17)#define PPC405_INTR_PPMI (_NTO_INTR_CLASS_EXTERNAL + 18)#define PPC405_INTR_EIR0I (_NTO_INTR_CLASS_EXTERNAL + 25)#define PPC405_INTR_EIR1I (_NTO_INTR_CLASS_EXTERNAL + 26)#define PPC405_INTR_EIR2I (_NTO_INTR_CLASS_EXTERNAL + 27)#define PPC405_INTR_EIR3I (_NTO_INTR_CLASS_EXTERNAL + 28)#define PPC405_INTR_EIR4I (_NTO_INTR_CLASS_EXTERNAL + 29)#define PPC405_INTR_EIR5I (_NTO_INTR_CLASS_EXTERNAL + 30)#define PPC405_INTR_EIR6I (_NTO_INTR_CLASS_EXTERNAL + 31)#define PPC440_INTR_UIC0_BASE (_NTO_INTR_CLASS_EXTERNAL)#define PPC440_INTR_U0 (PPC440_INTR_UIC0_BASE + 0)#define PPC440_INTR_U1 (PPC440_INTR_UIC0_BASE + 1)#define PPC440_INTR_IIC0 (PPC440_INTR_UIC0_BASE + 2)#define PPC440_INTR_IIC1 (PPC440_INTR_UIC0_BASE + 3)#define PPC440_INTR_PIM (PPC440_INTR_UIC0_BASE + 4)#define PPC440_INTR_PCRW (PPC440_INTR_UIC0_BASE + 5)#define PPC440_INTR_PPM (PPC440_INTR_UIC0_BASE + 6)#define PPC440_INTR_MSI0 (PPC440_INTR_UIC0_BASE + 7)#define PPC440_INTR_MSI1 (PPC440_INTR_UIC0_BASE + 8)#define PPC440_INTR_MSI2 (PPC440_INTR_UIC0_BASE + 9)#define PPC440_INTR_MTE (PPC440_INTR_UIC0_BASE + 10)#define PPC440_INTR_MRE (PPC440_INTR_UIC0_BASE + 11)#define PPC440_INTR_D0 (PPC440_INTR_UIC0_BASE + 12)#define PPC440_INTR_D1 (PPC440_INTR_UIC0_BASE + 13)#define PPC440_INTR_D2 (PPC440_INTR_UIC0_BASE + 14)#define PPC440_INTR_D3 (PPC440_INTR_UIC0_BASE + 15)#define PPC440_INTR_CT0 (PPC440_INTR_UIC0_BASE + 18)#define PPC440_INTR_CT1 (PPC440_INTR_UIC0_BASE + 19)#define PPC440_INTR_CT2 (PPC440_INTR_UIC0_BASE + 20)#define PPC440_INTR_CT3 (PPC440_INTR_UIC0_BASE + 21)#define PPC440_INTR_CT4 (PPC440_INTR_UIC0_BASE + 22)#define PPC440_INTR_EIR0 (PPC440_INTR_UIC0_BASE + 23)#define PPC440_INTR_EIR1 (PPC440_INTR_UIC0_BASE + 24)#define PPC440_INTR_EIR2 (PPC440_INTR_UIC0_BASE + 25)#define PPC440_INTR_EIR3 (PPC440_INTR_UIC0_BASE + 26)#define PPC440_INTR_EIR4 (PPC440_INTR_UIC0_BASE + 27)#define PPC440_INTR_EIR5 (PPC440_INTR_UIC0_BASE + 28)#define PPC440_INTR_EIR6 (PPC440_INTR_UIC0_BASE + 29)#define PPC440_INTR_UIC1NC (PPC440_INTR_UIC0_BASE + 30)#define PPC440_INTR_UIC1C (PPC440_INTR_UIC0_BASE + 31)#define PPC440_INTR_UIC1_BASE (_NTO_INTR_CLASS_EXTERNAL+32)#define PPC440_INTR_MS (PPC440_INTR_UIC1_BASE + 0)#define PPC440_INTR_MTDE (PPC440_INTR_UIC1_BASE + 1)#define PPC440_INTR_MRDE (PPC440_INTR_UIC1_BASE + 2)#define PPC440_INTR_DEUE (PPC440_INTR_UIC1_BASE + 3)#define PPC440_INTR_DECE (PPC440_INTR_UIC1_BASE + 4)#define PPC440_INTR_EBC0 (PPC440_INTR_UIC1_BASE + 5)#define PPC440_INTR_EBMI (PPC440_INTR_UIC1_BASE + 6)#define PPC440_INTR_OPB (PPC440_INTR_UIC1_BASE + 7)#define PPC440_INTR_MSI3 (PPC440_INTR_UIC1_BASE + 8)#define PPC440_INTR_MSI4 (PPC440_INTR_UIC1_BASE + 9)#define PPC440_INTR_MSI5 (PPC440_INTR_UIC1_BASE + 10)#define PPC440_INTR_MSI6 (PPC440_INTR_UIC1_BASE + 11)#define PPC440_INTR_MSI7 (PPC440_INTR_UIC1_BASE + 12)#define PPC440_INTR_MSI8 (PPC440_INTR_UIC1_BASE + 13)#define PPC440_INTR_MSI9 (PPC440_INTR_UIC1_BASE + 14)#define PPC440_INTR_MSI10 (PPC440_INTR_UIC1_BASE + 15)#define PPC440_INTR_MSI11 (PPC440_INTR_UIC1_BASE + 16)#define PPC440_INTR_PLBPM (PPC440_INTR_UIC1_BASE + 17)#define PPC440_INTR_EIR7 (PPC440_INTR_UIC1_BASE + 18)#define PPC440_INTR_EIR8 (PPC440_INTR_UIC1_BASE + 19)#define PPC440_INTR_EIR9 (PPC440_INTR_UIC1_BASE + 20)#define PPC440_INTR_EIR10 (PPC440_INTR_UIC1_BASE + 21)#define PPC440_INTR_EIR11 (PPC440_INTR_UIC1_BASE + 22)#define PPC440_INTR_EIR12 (PPC440_INTR_UIC1_BASE + 23)#define PPC440_INTR_SRE (PPC440_INTR_UIC1_BASE + 24)#define PPC440_INTR_PAE (PPC440_INTR_UIC1_BASE + 27)#define PPC440_INTR_ETH0 (PPC440_INTR_UIC1_BASE + 28)#define PPC440_INTR_EWU0 (PPC440_INTR_UIC1_BASE + 29)#define PPC440_INTR_ETH1 (PPC440_INTR_UIC1_BASE + 30)#define PPC440_INTR_EWU1 (PPC440_INTR_UIC1_BASE + 31)/* * On 440GX */#define PPC440_INTR_UIC2_BASE (_NTO_INTR_CLASS_EXTERNAL+64)#define PPC440_INTR_ETH2 (PPC440_INTR_UIC2_BASE + 0)#define PPC440_INTR_EWU2 (PPC440_INTR_UIC2_BASE + 1)#define PPC440_INTR_ETH3 (PPC440_INTR_UIC2_BASE + 2)#define PPC440_INTR_EWU3 (PPC440_INTR_UIC2_BASE + 3)#define PPC440_INTR_TAH0 (PPC440_INTR_UIC2_BASE + 4)#define PPC440_INTR_TAH1 (PPC440_INTR_UIC2_BASE + 5)#define PPC440_INTR_IMUOFQ (PPC440_INTR_UIC2_BASE + 6)#define PPC440_INTR_IMUIPQ (PPC440_INTR_UIC2_BASE + 7)#define PPC440_INTR_IMUIRD (PPC440_INTR_UIC2_BASE + 8)#define PPC440_INTR_IMUID (PPC440_INTR_UIC2_BASE + 9)#define PPC440_INTR_IMUIM0 (PPC440_INTR_UIC2_BASE + 10)#define PPC440_INTR_IMUIM1 (PPC440_INTR_UIC2_BASE + 11)#define PPC440_INTR_IMUTE (PPC440_INTR_UIC2_BASE + 12)#define PPC440_INTR_MSI12 (PPC440_INTR_UIC2_BASE + 13)#define PPC440_INTR_MSI13 (PPC440_INTR_UIC2_BASE + 14)#define PPC440_INTR_MSI14 (PPC440_INTR_UIC2_BASE + 15)#define PPC440_INTR_MSI15 (PPC440_INTR_UIC2_BASE + 16)#define PPC440_INTR_EIR13 (PPC440_INTR_UIC2_BASE + 17)#define PPC440_INTR_EIR14 (PPC440_INTR_UIC2_BASE + 18)#define PPC440_INTR_EIR15 (PPC440_INTR_UIC2_BASE + 19)#define PPC440_INTR_EIR16 (PPC440_INTR_UIC2_BASE + 20)#define PPC440_INTR_EIR17 (PPC440_INTR_UIC2_BASE + 21)#define PPC440_INTR_PVPD (PPC440_INTR_UIC2_BASE + 22)#define PPC440_INTR_L2C (PPC440_INTR_UIC2_BASE + 23)#define PPC440_INTR_ETH2PS (PPC440_INTR_UIC2_BASE + 24)#define PPC440_INTR_ETH3PS (PPC440_INTR_UIC2_BASE + 25) #define PPC440GX_INTR_UICB0_BASE (_NTO_INTR_CLASS_EXTERNAL+256)#define PPC440GX_INTR_UIC0C (PPC440GX_INTR_UICB0_BASE + 0)#define PPC440GX_INTR_UIC0NC (PPC440GX_INTR_UICB0_BASE + 1)#define PPC440GX_INTR_UIC1C (PPC440GX_INTR_UICB0_BASE + 2)#define PPC440GX_INTR_UIC1NC (PPC440GX_INTR_UICB0_BASE + 3)#define PPC440GX_INTR_UIC2C (PPC440GX_INTR_UICB0_BASE + 4)#define PPC440GX_INTR_UIC2NC (PPC440GX_INTR_UICB0_BASE + 5)/* 400 timer class */#define PPC_INTR_CLASS_400TIMER (0x8001UL<<16)#define PPC400_INTR_PI (PPC_INTR_CLASS_400TIMER + 0)#define PPC400_INTR_FI (PPC_INTR_CLASS_400TIMER + 1)#define PPC400_INTR_WI (PPC_INTR_CLASS_400TIMER + 2)#endif⌨️ 快捷键说明
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