pci.h

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */







/*
 *  pci.h
 *
 */
#ifndef __PCI_H_INCLUDED

#include <_pack1.h>

#ifndef __PLATFORM_H_INCLUDED
#include <sys/platform.h>
#endif

#ifndef _INTTYPES_H_INCLUDED
 #include <inttypes.h>
#endif

#ifndef __TYPES_H_INCLUDED
 #include <sys/types.h>
#endif

#ifndef	_STDDEF_H_INCLUDED
 #include	<stddef.h>
#endif

__BEGIN_DECLS

struct _pci_config_regs
{
        uint16_t          Vendor_ID;					/* 0x00 */
        uint16_t          Device_ID;					/* 0x02 */
        uint16_t          Command;						/* 0x04 */
        uint16_t          Status;						/* 0x06 */
        uint8_t           Revision_ID;					/* 0x08 */
        uint8_t           Class_Code[3];				/* 0x09 */
        uint8_t           Cache_Line_Size;				/* 0x0C */
        uint8_t           Latency_Timer;				/* 0x0D */
        uint8_t           Header_Type;					/* 0x0E */
        uint8_t           BIST;							/* 0x0F */
        uint32_t          Base_Address_Regs[6];			/* 0x10 */
        uint32_t          CardBus_CIS;					/* 0x28 */
		uint16_t          Sub_Vendor_ID;				/* 0x2C */
		uint16_t          Sub_System_ID;				/* 0x2E */
        uint32_t          ROM_Base_Address;				/* 0x30 */
		uint8_t           Capabilities_Pointer;			/* 0x34 */
		uint8_t           Reserved2 [3];				/* 0x35 */
        uint32_t          Reserved3;					/* 0x38 */
        uint8_t           Interrupt_Line;				/* 0x3C */
        uint8_t           Interrupt_Pin;				/* 0x3D */
        uint8_t           Min_Gnt;						/* 0x3E */
        uint8_t           Max_Lat;						/* 0x3F */
        uint8_t           Device_Dependent_Regs[192];
};

struct _pci_bridge_config_regs
{
        uint16_t          Vendor_ID;					/* 0x00 */
        uint16_t          Device_ID;					/* 0x02 */
        uint16_t          Command;						/* 0x04 */
        uint16_t          Status;						/* 0x06 */
        uint8_t           Revision_ID;					/* 0x08 */
        uint8_t           Class_Code[3];				/* 0x09 */
        uint8_t           Cache_Line_Size;				/* 0x0C */
        uint8_t           Latency_Timer;				/* 0x0D */
        uint8_t           Header_Type;					/* 0x0E */
        uint8_t           BIST;							/* 0x0F */
        uint32_t          Base_Address_Regs[2];			/* 0x10 */
		uint8_t           Primary_Bus_Number;			/* 0x18 */
		uint8_t           Secondary_Bus_Number;			/* 0x19 */
		uint8_t           Subordinate_Bus_Number;		/* 0x1A */
        uint8_t           Secondary_Latency_Timer;		/* 0x1B */
		uint8_t           IO_Base;						/* 0x1C */
		uint8_t           IO_Limit;						/* 0x1D */
		uint16_t          Secondary_Status;				/* 0x1E */
		uint16_t          Memory_Base;					/* 0x20 */
		uint16_t          Memory_Limit;					/* 0x22 */
		uint16_t          Prefetchable_Memory_Base;		/* 0x24 */
		uint16_t          Prefetchable_Memory_Limit;	/* 0x26 */
		uint32_t          Prefetchable_Base_Upper32;	/* 0x28 */
		uint32_t          Prefetchable_Limit_Upper32;	/* 0x2c */
		uint16_t          IO_Base_Upper16;				/* 0x30 */
		uint16_t          IO_Limit_Upper16;				/* 0x32 */
		uint8_t           Capabilities_Pointer;			/* 0x34 */
        uint8_t           Reserved1 [3];				/* 0x35 */
        uint32_t          ROM_Base_Address;				/* 0x38 */
        uint8_t           Interrupt_Line;				/* 0x3C */
        uint8_t           Interrupt_Pin;				/* 0x3D */
		uint16_t          Bridge_Control;				/* 0x3E */
        uint8_t           Device_Dependent_Regs[192];
};

struct _pci_cardbus_config_regs
{
        uint16_t           Vendor_ID;					/* 0x00 */
        uint16_t           Device_ID;					/* 0x02 */
        uint16_t           Command;						/* 0x04 */
        uint16_t           Status;						/* 0x06 */
        uint8_t            Revision_ID;					/* 0x08 */
        uint8_t            Class_Code[3];				/* 0x09 */
        uint8_t            Cache_Line_Size;				/* 0x0C */
        uint8_t            Latency_Timer;				/* 0x0D */
        uint8_t            Header_Type;					/* 0x0E */
        uint8_t            BIST;						/* 0x0F */
        uint32_t           Socket_Exca_Base_Reg;		/* 0x10 */
		uint8_t            Capabilities_Pointer;		/* 0x14 */
        uint8_t            reserved1;					/* 0x15 */
        uint16_t           Secondary_Status;			/* 0x16 */
        uint8_t            Pci_Bus_Num;					/* 0x18 */
        uint8_t            Cardbus_Bus_Num;				/* 0x19 */
        uint8_t            Sub_Bus_Num;					/* 0x1A */
        uint8_t            Cardbus_Latency_Timer;		/* 0x1B */
        uint32_t           Mem_Base_Reg_0;				/* 0x1C */
        uint32_t           Mem_Limit_Reg_0;				/* 0x20 */
        uint32_t           Mem_Base_Reg_1;				/* 0x24 */
        uint32_t           Mem_Limit_Reg_1;				/* 0x28 */
        uint32_t           Io_Base_Reg_0;				/* 0x2C */
        uint32_t           Io_Limit_Reg_0;				/* 0x30 */
        uint32_t           Io_Base_Reg_1;				/* 0x34 */
        uint32_t           Io_Limit_Reg_1;				/* 0x38 */
        uint8_t            Interrupt_Line;				/* 0x3C */
        uint8_t            Interrupt_Pin;				/* 0x3D */
        uint16_t           Bridge_Control;				/* 0x3E */
        uint16_t           Subsystem_Vendor_Id;			/* 0x40 */
        uint16_t           Subsystem_Id;				/* 0x42 */
        uint32_t           If_Legacy_Base_Reg;			/* 0x44 */
        uint8_t            reserved2[56];				/* 0x48 */
        uint32_t           System_Control;				/* 0x80 */
        uint8_t            reserved3[8];				/* 0x84 */
		uint32_t           Multifunction_Routing;		/* 0x8C */
        uint8_t            Retry_Status;				/* 0x90 */
        uint8_t            Card_Control;				/* 0x91 */
        uint8_t            Device_Control;				/* 0x92 */
        uint8_t            Buffer_Control;				/* 0x93 */
        uint32_t           Dma_Reg_0;					/* 0x94 */
        uint32_t           Dma_Reg_1;					/* 0x98 */
        uint8_t            Device_Dependent_Regs[100];
};


/* Power management capability - 0x01 */

struct	_pci_capability_power
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				Power_PMC;
		uint16_t				Power_PMCSR;
		uint8_t					Power_PMCSR_BSE;
		uint8_t					Power_Data;
};

/* Vital Product Data Capability - 0x03 */

struct	_pci_capability_vpd
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				VPD_Address;
		uint32_t				VPD_Data;
};

/* Slot Numbering capability - 0x04 */

struct	_pci_capability_slot_numbering
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint8_t					Card_Slot;
		uint8_t					Chassis_Number;
};

/* MSI capability for 32-bit message address - 0x05 */

struct	_pci_capability_msi32
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				Message_Control;
		uint32_t				Message_Address;
		uint16_t				Message_Data;
		uint16_t				Filler;
};

/* MSI capability for 64-bit message address - 0x05 */

struct	_pci_capability_msi64
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				Message_Control;
		uint32_t				Message_Address;
		uint32_t				Message_Address_Upper;
		uint16_t				Message_Data;
		uint16_t				Filler;
};

/* MSI capability for 32-bit message address and per-vector masking - 0x05 */

struct	_pci_capability_msi32_PVM
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				Message_Control;
		uint32_t				Message_Address;
		uint16_t				Message_Data;
		uint16_t				Filler;
		uint32_t				Mask_Bits;
		uint32_t				Pending_Bits;
};

/* MSI capability for 64-bit message address and per-vector masking - 0x05 */

struct	_pci_capability_msi64_PVM
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				Message_Control;
		uint32_t				Message_Address;
		uint32_t				Message_Address_Upper;
		uint16_t				Message_Data;
		uint16_t				Filler;
		uint32_t				Mask_Bits;
		uint32_t				Pending_Bits;
};

/* PCI-X capability - 0x07 */

struct	_pci_capability_pcix
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				PCI_X_Command;
		uint32_t				PCI_X_Status;
};

/* PCI-X bridge capability - 0x07 */

struct	_pci_capability_pcix_bridge
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				PCI_X_Secondary_Status;
		uint32_t				PCI_X_Bridge_Status;
		uint32_t				Upstream_Split_Transaction_Control;
		uint32_t				Downstream_Split_Transaction_Control;
};

/* PCI-Express capability - 0x10 */

struct	_pci_capability_pci_express
{
		uint8_t                 Capability_ID;
		uint8_t                 Next_Pointer;
		uint16_t				PCI_Express_Cap_Reg;
		uint32_t				Device_Capabilities;
		uint16_t				Device_Control;
		uint16_t				Device_Status;
		uint32_t				Link_Capabilities;
		uint16_t				Link_Control;
		uint16_t				Link_Status;
		uint32_t				Slot_Capabilities;
		uint16_t				Slot_Control;
		uint16_t				Slot_Status;
		uint16_t				Root_Control;
		uint16_t				Root_Capabilities;
		uint32_t				Root_Status;
};

/* HyperTransport Slave/Primary Interface Block Format */

struct	_pci_ht_sp_capability
{
		uint8_t					Capability_ID;
		uint8_t					Next_Pointer;
		uint16_t				Command;
		uint16_t				Link_Control0;
		uint16_t				Link_Config0;
		uint16_t				Link_Control1;
		uint16_t				Link_Config1;
		uint8_t					Revision_ID;
		uint8_t					Link_Freq_Error0;
		uint16_t				Link_Freq_Cap0;
		uint8_t					Feature;
		uint8_t					Link_Freq_Error1;
		uint16_t				Link_Freq_Cap1;
		uint16_t				Enumeration_Scratch;
		uint16_t				Error_Handling;
		uint8_t					Mem_Base_Upper;
		uint8_t					Mem_Limit_Upper;
		uint8_t					Bus_Number;
		uint8_t					Reserved;
};

/* HyperTransport Host/Secondary Interface Block Format */

struct	_pci_ht_hs_capability
{
		uint8_t					Capability_ID;
		uint8_t					Next_Pointer;
		uint16_t				Command;
		uint16_t				Link_Control;
		uint16_t				Link_Config;
		uint8_t					Revision_ID;
		uint8_t					Link_Freq_Error;
		uint16_t				Link_Freq_Cap;
		uint16_t				Feature;
		uint16_t				Reserved;
		uint16_t				Enumeration_Scratch;
		uint16_t				Error_Handling;
		uint8_t					Mem_Base_Upper;
		uint8_t					Mem_Limit_Upper;
		uint16_t				Reserved2;
};

/*
 * Command Register; contains command and capability fields.
 */
#define HT_COMMAND_CAP_OFF    		0x00

#define HT_CAP_ID_MASK         		0x000000FF
#define HT_CAP_ID_SHIFT        		0
#define HT_CAP_PTR_MASK        		0x0000FF00
#define HT_CAP_PTR_SHIFT       		8

#define HT_COMMAND_MASK				0xFFFF0000
#define HT_COMMAND_SHIFT			16
#define HT_COMMAND(cmd) (((cmd) & HT_COMMAND_MASK) >> HT_COMMAND_SHIFT)
#define HT_COMMAND_TYPE_MASK		0xE0000000
#define HT_COMMAND_TYPE_SHIFT		(29)
#define HT_COMMAND_TYPE(cmd) (((cmd) & HT_COMMAND_TYPE_MASK) >> HT_COMMAND_TYPE_SHIFT)
#define HT_COMMAND_TYPE_SLAVE		0x0
#define HT_COMMAND_TYPE_HOST		0x1
#define HT_COMMAND_TYPE_SWITCH		0x2   /* extended in 1.05 */
#define HT_COMMAND_TYPE_IDC			0x4   /* ditto */
#define HT_COMMAND_TYPE_AMAP		0x5   /* ditto */

/*
 * An HT capability for type Slave (aka Primary, aka "tunnel") consists
 * of a Command register, two Link registers, and two Freq/Rev registers.
 */
/* Slave/Primary commands */
#define HT_COMMAND_UNIT_ID_MASK         	0x001F0000
#define HT_COMMAND_UNIT_ID_SHIFT        	(16)
#define HT_COMMAND_UNIT_ID(cmd) \
	(((cmd) & HT_COMMAND_UNIT_ID_MASK) >> HT_COMMAND_UNIT_ID_SHIFT)
#define HT_COMMAND_UNIT_COUNT_MASK        	0x03E00000
#define HT_COMMAND_UNIT_COUNT_SHIFT       	(21)
#define HT_COMMAND_UNIT_COUNT(cmd) \
	(((cmd) & HT_COMMAND_UNIT_COUNT_MASK) >> HT_COMMAND_UNIT_COUNT_SHIFT)
#define HT_COMMAND_MASTER_HOST_MASK			0x04000000
#define HT_COMMAND_MASTER_HOST(cmd) \
	(((cmd) & HT_COMMAND_MASTER_HOST_MASK) ? 1 : 0)
#define HT_COMMAND_DEFAULT_DIRECTION_MASK	0x08000000
#define HT_COMMAND_DEFAULT_DIRECTION(cmd) \
	(((cmd) & HT_COMMAND_DEFAULT_DIRECTION_MASK) ? 1 : 0)

/*
 * An HT capability for type Host (aka Secondary) consists of a
 * Command register, a single Link register, and a Freq/Rev register.
 */
/* Host/Secondary command fields */
#define HT_COMMAND_WARM_RESET				0x00010000
#define HT_COMMAND_DOUBLE_ENDED				0x00020000
#define HT_COMMAND_DEVICE_NUMBER_MASK		0x007C0000