amd_poll.c

qnx powerpc MPC8245的 BSP源文件

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $ 
 */



#include <sys/f3s_mtd.h>

/*
 * Description
 *
 * This is not a valid MTD callout. For internal use by other MTD callouts.
 */

int amd_poll(volatile void *memory, int dq1)
{
	uintptr_t		amd_cmd1;
	uintptr_t		amd_cmd2;
	F3S_BASETYPE	status[2];
	F3S_BASETYPE	mask6 = (1 << 6) * flashcfg.device_mult;
	F3S_BASETYPE	mask;
	F3S_BASETYPE	toggle;


	/* Wait for 6 us - according to AMD document, the maximam delay is 4 us */
	nanospin_ns(6000);

	/* Poll for write completion */
	status[1] = readmem(memory);
	while (1) {
		/* Cycle the old status around so we only need to read once */
		status[0] = status[1];
		status[1] = readmem(memory);

		/* Stop if DQ6 has stopped toggling */
		toggle = (status[0] ^ status[1]) & mask6;
		if (!toggle) break;

		/* If DQ5 is *only* set on the chips that are still toggling */
		mask = (status[0] & (toggle >> 1)) << 1;
		if (mask == toggle) {
			/* Poll again */
			status[0] = status[1];
			status[1] = readmem(memory);

			/* If *any* of the same DQ6 bits are still toggling */
			if ((status[0] ^ status[1]) & mask) {
				/*
				 * At this point we know that any good writes have finished
				 */

				/* We have an error, reset */
				send_command(memory, AMD_READ_MODE);

				/* Wait for 6 us - according to AMD document, the maximam delay is 4 us */
				nanospin_ns(6000);

				return (-1);
			}

			/* Otherwise, DQ6 has stopped toggling */

		/* If this chip supports DQ1 errors */
		} else if (dq1) {
			/* If DQ1 is *only* set on the chips that are still toggling */
			mask = (status[0] & (toggle >> 5)) << 5;
			if (mask == toggle) {
				/* Poll again */
				status[0] = status[1];
				status[1] = readmem(memory);

				/* If *any* of the same DQ6 bits are still toggling */
				if ((status[0] ^ status[1]) & mask) {
					/*
					 * At this point we know that any good writes have finished
					 */

					if (flashcfg.device_width == 1) {
						amd_cmd1 = AMD_CMD_ADDR1_W8;
						amd_cmd2 = AMD_CMD_ADDR2_W8;
					} else {
						amd_cmd1 = AMD_CMD_ADDR1_W16;
						amd_cmd2 = AMD_CMD_ADDR2_W16;
					}
					amd_cmd1 *= flashcfg.bus_width;
					amd_cmd2 *= flashcfg.bus_width;

					/* We have an error, reset */
					send_command(memory + amd_cmd1, AMD_UNLOCK_CMD1);

					/* Wait for 6 us - according to AMD document, the maximam delay is 4 us */
					nanospin_ns(6000);

					send_command(memory + amd_cmd2, AMD_UNLOCK_CMD2);

					/* Wait for 6 us - according to AMD document, the maximam delay is 4 us */
					nanospin_ns(6000);
					send_command(memory + amd_cmd1, AMD_READ_MODE);

					/* Wait for 6 us - according to AMD document, the maximam delay is 4 us */
					nanospin_ns(6000);
					return (-1);
				}
			}
		}
	}

	return (0);
}