ncsim.log

spi总线控制器的fpga实现 verilog源代码及测试

ncsim: v03.40.(b001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
ncsim: *F,MISSIM: missing simulation name.
ncsim: Memory Usage - 4.5M program + 0.2M data = 4.7M total
ncsim: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 100.0% cpu)