71x_init.s

来自「基于Arm Developer suite 1.2开发」· S 代码 · 共 79 行

			AREA	Init, CODE, READONLY

Stack_Base	EQU		0x20010000

FIQ_StkLen	EQU		512
IRQ_StkLen	EQU		512

FIQ_StkOfs	EQU		0
IRQ_StkOfs	EQU		FIQ_StkOfs + FIQ_StkLen
SVC_StkOfs	EQU		IRQ_StkOfs + IRQ_StkLen

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

No_INT		EQU		0xC0
Mode_FIQ	EQU		0x11
Mode_IRQ	EQU		0x12
Mode_SVC	EQU		0x13


; --- System memory locations

GPIO0_Base	EQU		0xE0003000
PC0_off		EQU		0x00
PC1_off		EQU		0x04
PC2_off		EQU		0x08
PD_off		EQU		0x0C

			ENTRY

			EXPORT	Reset_Handler
Reset_Handler
; Reset SSIG
			LDR		r0, =GPIO0_Base
			LDRH	r2, [r0, #PD_off]
			BIC		r2, r2,#0x00000020
			STRH	r2, [r0, #PD_off]
			LDRH	r2, [r0, #PC0_off]
			ORR		r2, r2,#0x00000020
			STRH	r2, [r0, #PC0_off]
			LDRH	r2, [r0, #PC1_off]
			BIC		r2, r2,#0x00000020
			STRH	r2, [r0, #PC1_off]
			LDRH	r2, [r0, #PC2_off]
			ORR		r2, r2,#0x00000020
			STRH	r2, [r0, #PC2_off]

; Setup stacks
			LDR		r0, =Stack_Base
			MSR		CPSR_c, #No_INT | Mode_FIQ
			SUB		sp, r0, #FIQ_StkOfs
			MSR		CPSR_c, #No_INT | Mode_IRQ
			SUB		sp, r0, #IRQ_StkOfs
			MSR		CPSR_c, #No_INT | Mode_SVC
			SUB		sp, r0, #SVC_StkOfs

			MSR		CPSR_c, #Mode_SVC

			IMPORT	__main
			BL		__main

			IMPORT	|Image$$ZI$$Limit|
			EXPORT	__user_initial_stackheap
__user_initial_stackheap
			LDR		r0, =|Image$$ZI$$Limit|
			MOV		pc, lr

	IF {TRUE}
			IMPORT	__use_no_semihosting_swi
			EXPORT	_ttywrch
			EXPORT	_sys_exit
_ttywrch
_sys_exit
			B		.
	ENDIF

			LTORG

			END