bsp.c

这是用IAR开发的AT91SAM7X256的CAN测试代码

        (*pfnct)();                                 /* Execute the ISR for the interrupting device     */
    }
#else
    pfnct = (BSP_PFNCT)AT91C_BASE_AIC->AIC_IVR;     /* Read the interrupt vector from the VIC          */
    while (pfnct != (BSP_PFNCT)0) {                 /* Make sure we don't have a NULL pointer          */
      (*pfnct)();                                   /* Execute the ISR for the interrupting device     */
        pfnct = (BSP_PFNCT)AT91C_BASE_AIC->AIC_IVR; /* Read the interrupt vector from the VIC          */
    }
#endif
}

/*
*********************************************************************************************************
*                                           FIQ ISR HANDLER
*
* Description : This function is called by OS_CPU_FIQ_ISR() to determine the source of the interrupt
*               and process it accordingly.
*
* Arguments   : none
*********************************************************************************************************
*/

void  OS_CPU_FIQ_ISR_Handler (void)
{
    BSP_PFNCT  pfnct;

#if 1
    pfnct = (BSP_PFNCT)AT91C_BASE_AIC->AIC_FVR;     /* Read the interrupt vector from the VIC               */
    if (pfnct != (BSP_PFNCT)0) {                    /* Make sure we don't have a NULL pointer               */
        (*pfnct)();                                 /* Execute the ISR for the interrupting device          */
    }
#else
    pfnct = (BSP_PFNCT)AT91C_BASE_AIC->AIC_FVR;     /* Read the interrupt vector from the VIC               */
    while (pfnct != (BSP_PFNCT)0) {                 /* Make sure we don't have a NULL pointer               */
      (*pfnct)();                                   /* Execute the ISR for the interrupting device          */
        pfnct = (BSP_PFNCT)AT91C_BASE_AIC->AIC_FVR; /* Read the interrupt vector from the VIC               */
    }
#endif
}

/*
*********************************************************************************************************
*                                         TICKER INITIALIZATION
*
* Description : This function is called to initialize uC/OS-II's tick source which uses the PIT
*               (typically a timer generating interrupts every 1 to 100 mS).
*
* Arguments   : none
*
* Note(s)     : 1) PIT Interrupt frequency:
*
*                         MCLK        1
*               Freq =    ---- * -----------
*                          16     (PIV + 1)
*
*
*                         MCLK      1
*               PIV  =  ( ---- * ------ ) - 1
*                          16     Freq
*
*               Where:
*                    MCLK = 48 MHz (i.e 48,000,000)
*                    Freq = Desired frequency (i.e. OS_TICKS_PER_SEC)
*********************************************************************************************************
*/

static  void  Tmr_TickInit (void)
{
    INT32U  counts;

                                                /* Set the vector address for PIT                      */
    AT91C_BASE_AIC->AIC_SVR[AT91C_ID_SYS] = (INT32U)Tmr_TickISR_Handler;// OS_CPU_IRQ_ISR;
    AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS] = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE
                                          | AT91C_AIC_PRIOR_LOWEST;
    AT91C_BASE_AIC->AIC_ICCR              = 1 << AT91C_ID_SYS;
    AT91C_BASE_AIC->AIC_IECR              = 1 << AT91C_ID_SYS;

    counts                                = (48000000 / 16 / OS_TICKS_PER_SEC) - 1;
	AT91C_BASE_PITC->PITC_PIMR            = AT91C_PITC_PITEN | AT91C_PITC_PITIEN | counts;
}
/*
*********************************************************************************************************
*                                           PIT IRQ HANDLER
*
* Description : This function handles the PIT interrupt that is used to generate TICKs for uC/OS-II.
*
* Arguments   : none
*********************************************************************************************************
*/

#ifdef EXTBSP_H

static  void  Tmr_TickISR_Handler (void)
{
     volatile static INT32U  status;
	
    AT91C_BASE_AIC->AIC_IVR   = 0;            /* Debug variant of vector read (protect mode is used)   */
    AT91C_BASE_AIC->AIC_ICCR  = AT91C_ID_SYS; /* Clear  timer #0 interrupt                             */
   	AT91C_BASE_AIC->AIC_EOICR = 0;            /* Signal end of interrupt                               */

	if((AT91PS_PITC)AT91C_BASE_PITC->PITC_PISR)
    {
    	status                    = AT91C_BASE_PITC->PITC_PIVR;
    	OSTimeTick();                             /* Tell uC/OS-II about clock tick                        */
	}
	else
	{
		if((int)((AT91PS_DBGU)AT91C_BASE_DBGU->DBGU_CSR) & (int)0x01)
		{
			if(pRxdt==&RXDT[19])
			{
				pRxdt=RXDT;
			}
			*(++pRxdt)=(int)(AT91PS_DBGU)AT91C_BASE_DBGU->DBGU_RHR;
			OSSemPost (pE_Key);
		}
	}
}
#else

static  void  Tmr_TickISR_Handler (void)
{
     volatile static INT32U  status;
	
    AT91C_BASE_AIC->AIC_IVR   = 0;
    AT91C_BASE_AIC->AIC_ICCR  = AT91C_ID_SYS;
   	AT91C_BASE_AIC->AIC_EOICR = 0;

   	status = AT91C_BASE_PITC->PITC_PIVR;
   	OSTimeTick();
}
#endif
//---------------------------------------------------------------------------------------------------------
void  time_delay(int  dly)
{
	int  i;
	for(; dly>0; dly--)
		for(i=0; i<500; i++);
}




//------------------------------------------------------------------------------------------------------------

static  void CAN_Init()
{
//     AT91F_DBGU_Printk("\r\n Now Init CAN Interface\n");

     // Enable CAN PIOs
    AT91F_CAN_CfgPIO();
    // Enable CAN Clock
    AT91F_CAN_CfgPMC();

    // Enable CAN Transceiver
    AT91F_PIOA_CfgPMC();

    AT91F_PIO_CfgOutput(AT91C_BASE_PIOA,AT91B_CAN_TRANSCEIVER_RS) ;
    // Clear PA23 <=> Enable Transceiver Normal Mode (versus Standby mode)
    AT91F_PIO_ClearOutput(AT91C_BASE_PIOA,AT91B_CAN_TRANSCEIVER_RS) ;

//    AT91F_DBGU_Printk("\n\r Now Register CAN Interrupt Vector.\n");

    // Init CAN Interrupt Source Level
/*    AT91F_AIC_ConfigureIt(AT91C_BASE_AIC,                        	// CAN base address
                        AT91C_ID_CAN,                         	// CAN ID
                        AT91C_AIC_PRIOR_HIGHEST,               	// Max priority
                        AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, 	// Level sensitive
                        AT91F_CAN_Handler);                     // C Handler
*/


    AT91C_BASE_AIC->AIC_SVR[AT91C_ID_CAN] = (INT32U)AT91F_CAN_Handler;           // OS_CPU_IRQ_ISR;
    AT91C_BASE_AIC->AIC_SMR[AT91C_ID_CAN] = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE
                                          | AT91C_AIC_PRIOR_HIGHEST;
    AT91C_BASE_AIC->AIC_ICCR              = 1 << AT91C_ID_CAN;
    AT91C_BASE_AIC->AIC_IECR              = 1 << AT91C_ID_CAN;
//    AT91F_DBGU_Printk("\n\r Now Set CAN Baudrate.\n");
//125kbps
    AT91F_CAN_CfgBaudrateReg(AT91C_BASE_CAN,
                           0x1  << 24  |         // SMP = 0, sampled once at sample point
                           0x17 << 16  |         // BRP = 23 =0x17
                           0x3  << 12  |         // SJW = 3
                           0x0  << 8   |         // PROPAG = 0
                           0x6  << 4   |         // PHASE1 = 6
                           0x6  << 0);           // PHASE2 = 6
/*
//50kbps
    AT91F_CAN_CfgBaudrateReg(AT91C_BASE_CAN,
                           0x1  << 24  |         // SMP = 0, sampled once at sample point
                           0x5F << 16  |         // BRP = 23 =0x17
                           0x2  << 12  |         // SJW = 3
                           0x0  << 8   |         // PROPAG = 0
                           0x3  << 4   |         // PHASE1 = 6
                           0x3  << 0);           // PHASE2 = 6
*/
}