ad99854.vhd

ＡＤ９９５４芯片控制软件

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:01:05 02/22/2008 
-- Design Name: 
-- Module Name:    ad99854 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ad99854 is
    Port ( input : in  STD_LOGIC_VECTOR (2 downto 0);
			  clk25m : in STD_LOGIC;
           sclk : out  STD_LOGIC;
           cs : out  STD_LOGIC;
           sdio : out  STD_LOGIC;
           reset : out  STD_LOGIC;
           updata : out  STD_LOGIC);
end ad99854;

architecture Behavioral of ad99854 is
signal input_data	: STD_LOGIC_VECTOR(2 downto 0):="010";
signal cnt_pll1 	: integer range 0 to 20000:=0;
signal ftw0_data  : STD_LOGIC_VECTOR(39 downto 0);
signal ftw0       : STD_LOGIC_VECTOR(39 downto 0);
signal cfr1_data  : STD_LOGIC_VECTOR(39 downto 0);
signal cfr2_data  : STD_LOGIC_VECTOR(31 downto 0);
begin
cfr1_data<="0000000000000000000000000000000000000000";
cfr2_data<="00000001000000000000000010100100";--20  200MHz
ftw0<="0000010000001100111111101100010101101101";--10.1525MHz
--reset<='0';
process(clk25m,input)
begin
  if clk25m'event and clk25m='1' then
	   if input=input_data then
         cnt_pll1<=19000;--16300;--stop
      else
         cnt_pll1<=16000;--13500;--begin;
      end if;
      if cnt_pll1=20000 then
         input_data<=input;
      else
         cnt_pll1<=cnt_pll1+1; 
      end if; 
  end if;	
  for i in 0 to 39 loop
	----------------------cfr1-----------------------------------
		if cnt_pll1>10020+30*i and cnt_pll1<=10050+30*i then		
			sdio<=cfr1_data(39-i);	
			if cnt_pll1>10030+30*i and cnt_pll1<=10040+30*i then
				sclk<='1';
			else
				sclk<='0';
			end if;
		end if;
  end loop;
  for j in 0 to 31 loop
	-----------------------cfr2--------------------------------
		if cnt_pll1>12020+30*j and cnt_pll1<=12050+30*j then		--
			sdio<=cfr2_data(31-j);	
			if cnt_pll1>12030+30*j and cnt_pll1<=12040+30*j then
				sclk<='1';
			else
				sclk<='0';
			end if;
		end if;	
  end loop;
  for k in 0 to 39 loop
	-----------------------ftw0--------------------------------
		if cnt_pll1>14020+30*k and cnt_pll1<=14050+30*k then		--
			sdio<=ftw0(39-k);	
			if cnt_pll1>14030+30*k and cnt_pll1<=14040+30*k then
				sclk<='1';
			else
				sclk<='0';
			end if;
		end if;	
  end loop;
	-----------------------ftw0_data--------------------------------
    for l in 0 to 39 loop
		if cnt_pll1>17020+30*l and cnt_pll1<=17050+30*l then		--
			sdio<=ftw0_data(39-l);	
			if cnt_pll1>17030+30*l and cnt_pll1<=17040+30*l then
				sclk<='1';
			else 
				sclk<='0';
			end if;
		end if;	
  end loop;  
  ---------------------------------------------------------------
  if cnt_pll1<=1000 then
    updata<='0';
	 reset<='1';
	 cs<='1';
--	 sclk<='1';
	 sdio<='1';
  elsif cnt_pll1>1000 and cnt_pll1<=2000 then
    updata<='0';
	 reset<='0';
	 cs<='1';
--	 sclk<='1';
	 sdio<='1';
  elsif cnt_pll1>2000 and cnt_pll1<=3000 then
    updata<='0';
	 reset<='0';
	 cs<='0';
--	 sclk<='1';
	 sdio<='1';
  elsif cnt_pll1>3000 and cnt_pll1<=4000 then
    updata<='0';
	 reset<='0';
	 cs<='0';
--	 sclk<='0';
	 sdio<='1';
  elsif cnt_pll1>9020 and cnt_pll1<=10020 then
    updata<='0';
	 reset<='0';
	 cs<='0';
--	 sclk<='0';
	 sdio<='0';
-------------------------------------------------------------
  elsif cnt_pll1>15520 and cnt_pll1<=15820 then
    updata<='1';
	 cs<='0';
  elsif cnt_pll1>15820 and cnt_pll1<=16000 then
    updata<='1';
	 cs<='1';
 --------------------------------------------------------
 elsif cnt_pll1>16000 and cnt_pll1<=16100 then
    updata<='0';
--	 reset<='1';
	 cs<='1';
--	 sclk<='1';
	 sdio<='1';
  elsif cnt_pll1>16100 and cnt_pll1<=16200 then
    updata<='0';
	 reset<='0';
	 cs<='1';
--	 sclk<='1';
	 sdio<='1';
  elsif cnt_pll1>16200 and cnt_pll1<=16300 then
    updata<='0';
	 reset<='0';
	 cs<='0';
--	 sclk<='1';
	 sdio<='1';
  elsif cnt_pll1>16300 and cnt_pll1<=16400 then
    updata<='0';
	 reset<='0';
	 cs<='0';
--	 sclk<='0';
	 sdio<='1';
  elsif cnt_pll1>16400 and cnt_pll1<=17020 then
    updata<='0';
	 reset<='0';
	 cs<='0';
--	 sclk<='0';
	 sdio<='0';
 ------------------------------------------------------------
  elsif cnt_pll1>18500 and cnt_pll1<=19000 then
    updata<='1';
	 cs<='0';
  elsif cnt_pll1>19000 and cnt_pll1<=20000 then
    updata<='1';
	 cs<='1';
 ------------------------------------------------------------
  end if;  
  case input is
      when "000"=>ftw0_data<="0000010000001100111111101100010101101101";--10.1525MHz
		when "001"=>ftw0_data<="0000010000001010111101100010101101101010";--8.56375MHz
		when "010"=>ftw0_data<="0000010000001100110011001100110011001100";--10.0MHz
		when "011"=>ftw0_data<="0000010000001011100011010100111111011111";--9.025MHz
		when "100"=>ftw0_data<="0000010000001100001010001111010111000010";--9.5MHz
		when "101"=>ftw0_data<="0000010000001100101000111101011100001010";--9.875MHz
		when "110"=>ftw0_data<="0000010000001011001100110011001100110011";--8.75MHz
		when "111"=>ftw0_data<="0000010000001011011101001011110001101010";--8.95MHz
		when others=>ftw0_data<="0000010000001100111111101100010101101101";
  end case;
end process; 
end Behavioral;