reg_16.vhd

8位十进制乘法器

library ieee;   -- 16位移位寄存器  
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity reg_16 is          
port(r16_clk,clr,r16_clr:in std_logic;
           r16_in:in std_logic_vector(8 downto 0);
           cout:out std_logic;
           r16_out:out std_logic_vector(15 downto 0));
end reg_16;
architecture arc_reg_16 of reg_16 is    
  signal reg16:std_logic_vector(15 downto 0);  
  signal i: std_logic_vector(3 downto 0);
  begin 
   process(r16_clk,r16_clr)  
     begin
      if clr='1'then cout<='0';reg16<="0000000000000000";
       elsif r16_clr='1' then               
         reg16<="0000000000000000"; cout<='0';i<="0000"; 
           elsif r16_clk'event and r16_clk='1' then 
              if (i="1000") then reg16<=reg16;cout<='1';
             else 
                 reg16(6 downto 0)<=reg16(7 downto 1);  
                  reg16(15 downto 7)<=r16_in; 
                  i<=i+1;   
             end if;
       end if;
   end process;
   r16_out<=reg16;    
end arc_reg_16;