multi_8x8.tan.qmsg

来自「8位十进制乘法器」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_a1 " "Info: Assuming node \"clk_a1\" is an undefined clock" {  } { { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_a1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_a0 " "Info: Assuming node \"clk_a0\" is an undefined clock" {  } { { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_a0" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_b1 " "Info: Assuming node \"clk_b1\" is an undefined clock" {  } { { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_b1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_b0 " "Info: Assuming node \"clk_b0\" is an undefined clock" {  } { { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_b0" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}