📄 reg_8.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "r8_clk register register reg8\[7\] reg8\[6\] 200.0 MHz Internal " "Info: Clock \"r8_clk\" Internal fmax is restricted to 200.0 MHz between source register \"reg8\[7\]\" and destination register \"reg8\[6\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.300 ns + Longest register register " "Info: + Longest register to register delay is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg8\[7\] 1 REG LC8_A21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A21; Fanout = 1; REG Node = 'reg8\[7\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { reg8[7] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 1.300 ns reg8\[6\] 2 REG LC6_A21 1 " "Info: 2: + IC(0.300 ns) + CELL(1.000 ns) = 1.300 ns; Loc. = LC6_A21; Fanout = 1; REG Node = 'reg8\[6\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "1.300 ns" { reg8[7] reg8[6] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns 76.92 % " "Info: Total cell delay = 1.000 ns ( 76.92 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 23.08 % " "Info: Total interconnect delay = 0.300 ns ( 23.08 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "1.300 ns" { reg8[7] reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { reg8[7] reg8[6] } { 0.000ns 0.300ns } { 0.000ns 1.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r8_clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"r8_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r8_clk 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { r8_clk } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns reg8\[6\] 2 REG LC6_A21 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_A21; Fanout = 1; REG Node = 'reg8\[6\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "0.400 ns" { r8_clk reg8[6] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[6] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r8_clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"r8_clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r8_clk 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { r8_clk } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns reg8\[7\] 2 REG LC8_A21 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_A21; Fanout = 1; REG Node = 'reg8\[7\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "0.400 ns" { r8_clk reg8[7] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[6] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "1.300 ns" { reg8[7] reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.300 ns" { reg8[7] reg8[6] } { 0.000ns 0.300ns } { 0.000ns 1.000ns } } } { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[6] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { reg8[6] } { } { } } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "reg8\[6\] r8_in\[6\] r8_clk 6.500 ns register " "Info: tsu for register \"reg8\[6\]\" (data pin = \"r8_in\[6\]\", clock pin = \"r8_clk\") is 6.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.300 ns + Longest pin register " "Info: + Longest pin to register delay is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns r8_in\[6\] 1 PIN PIN_101 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_101; Fanout = 1; PIN Node = 'r8_in\[6\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { r8_in[6] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.000 ns) 8.300 ns reg8\[6\] 2 REG LC6_A21 1 " "Info: 2: + IC(2.400 ns) + CELL(1.000 ns) = 8.300 ns; Loc. = LC6_A21; Fanout = 1; REG Node = 'reg8\[6\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "3.400 ns" { r8_in[6] reg8[6] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.900 ns 71.08 % " "Info: Total cell delay = 5.900 ns ( 71.08 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns 28.92 % " "Info: Total interconnect delay = 2.400 ns ( 28.92 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "8.300 ns" { r8_in[6] reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.300 ns" { r8_in[6] r8_in[6]~out reg8[6] } { 0.000ns 0.000ns 2.400ns } { 0.000ns 4.900ns 1.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r8_clk destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"r8_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r8_clk 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { r8_clk } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns reg8\[6\] 2 REG LC6_A21 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_A21; Fanout = 1; REG Node = 'reg8\[6\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "0.400 ns" { r8_clk reg8[6] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[6] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "8.300 ns" { r8_in[6] reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.300 ns" { r8_in[6] r8_in[6]~out reg8[6] } { 0.000ns 0.000ns 2.400ns } { 0.000ns 4.900ns 1.000ns } } } { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[6] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "r8_clk r8_out reg8\[0\] 10.600 ns register " "Info: tco from clock \"r8_clk\" to destination pin \"r8_out\" through register \"reg8\[0\]\" is 10.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r8_clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"r8_clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r8_clk 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { r8_clk } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns reg8\[0\] 2 REG LC7_A21 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_A21; Fanout = 1; REG Node = 'reg8\[0\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "0.400 ns" { r8_clk reg8[0] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns + Longest register pin " "Info: + Longest register to pin delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg8\[0\] 1 REG LC7_A21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A21; Fanout = 1; REG Node = 'reg8\[0\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { reg8[0] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(6.300 ns) 7.700 ns r8_out 2 PIN PIN_8 0 " "Info: 2: + IC(1.400 ns) + CELL(6.300 ns) = 7.700 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'r8_out'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "7.700 ns" { reg8[0] r8_out } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 81.82 % " "Info: Total cell delay = 6.300 ns ( 81.82 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 18.18 % " "Info: Total interconnect delay = 1.400 ns ( 18.18 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "7.700 ns" { reg8[0] r8_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.700 ns" { reg8[0] r8_out } { 0.000ns 1.400ns } { 0.000ns 6.300ns } } } } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "7.700 ns" { reg8[0] r8_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.700 ns" { reg8[0] r8_out } { 0.000ns 1.400ns } { 0.000ns 6.300ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "reg8\[0\] r8_load r8_clk 0.400 ns register " "Info: th for register \"reg8\[0\]\" (data pin = \"r8_load\", clock pin = \"r8_clk\") is 0.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r8_clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"r8_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r8_clk 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { r8_clk } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns reg8\[0\] 2 REG LC7_A21 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_A21; Fanout = 1; REG Node = 'reg8\[0\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "0.400 ns" { r8_clk reg8[0] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r8_load 1 PIN PIN_124 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 8; PIN Node = 'r8_load'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "" { r8_load } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.800 ns) 3.300 ns reg8\[0\] 2 REG LC7_A21 1 " "Info: 2: + IC(0.500 ns) + CELL(0.800 ns) = 3.300 ns; Loc. = LC7_A21; Fanout = 1; REG Node = 'reg8\[0\]'" { } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "1.300 ns" { r8_load reg8[0] } "NODE_NAME" } "" } } { "reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 84.85 % " "Info: Total cell delay = 2.800 ns ( 84.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns 15.15 % " "Info: Total interconnect delay = 0.500 ns ( 15.15 % )" { } { } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "3.300 ns" { r8_load reg8[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.300 ns" { r8_load r8_load~out reg8[0] } { 0.000ns 0.000ns 0.500ns } { 0.000ns 2.000ns 0.800ns } } } } 0} } { { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "2.400 ns" { r8_clk reg8[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r8_clk r8_clk~out reg8[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_8/db/reg_8_cmp.qrpt" Compiler "reg_8" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_8/db/reg_8.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_8/" "" "3.300 ns" { r8_load reg8[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.300 ns" { r8_load r8_load~out reg8[0] } { 0.000ns 0.000ns 0.500ns } { 0.000ns 2.000ns 0.800ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 19 15:45:57 2012 " "Info: Processing ended: Wed Dec 19 15:45:57 2012" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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