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📄 reg_8.fit.eqn

📁 8位十进制乘法器
💻 EQN
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--reg8[0] is reg8[0] at LC7_A21
--operation mode is normal

reg8[0]_lut_out = r8_load & r8_in[0] # !r8_load & (reg8[1]);
reg8[0] = DFFEA(reg8[0]_lut_out, GLOBAL(r8_clk), !GLOBAL(clr), , , , );

--A1L61Q is reg8[0]~36 at LC7_A21
--operation mode is normal

A1L61Q = reg8[0];


--reg8[1] is reg8[1] at LC1_A21
--operation mode is normal

reg8[1]_lut_out = r8_load & r8_in[1] # !r8_load & (reg8[2]);
reg8[1] = DFFEA(reg8[1]_lut_out, GLOBAL(r8_clk), !GLOBAL(clr), , , , );

--A1L81Q is reg8[1]~37 at LC1_A21
--operation mode is normal

A1L81Q = reg8[1];


--reg8[2] is reg8[2] at LC2_A21
--operation mode is normal

reg8[2]_lut_out = r8_load & r8_in[2] # !r8_load & (reg8[3]);
reg8[2] = DFFEA(reg8[2]_lut_out, GLOBAL(r8_clk), !GLOBAL(clr), , , , );

--A1L02Q is reg8[2]~38 at LC2_A21
--operation mode is normal

A1L02Q = reg8[2];


--reg8[3] is reg8[3] at LC3_A21
--operation mode is normal

reg8[3]_lut_out = r8_load & r8_in[3] # !r8_load & (reg8[4]);
reg8[3] = DFFEA(reg8[3]_lut_out, GLOBAL(r8_clk), !GLOBAL(clr), , , , );

--A1L22Q is reg8[3]~39 at LC3_A21
--operation mode is normal

A1L22Q = reg8[3];


--reg8[4] is reg8[4] at LC4_A21
--operation mode is normal

reg8[4]_lut_out = r8_load & r8_in[4] # !r8_load & (reg8[5]);
reg8[4] = DFFEA(reg8[4]_lut_out, GLOBAL(r8_clk), !GLOBAL(clr), , , , );

--A1L42Q is reg8[4]~40 at LC4_A21
--operation mode is normal

A1L42Q = reg8[4];


--reg8[5] is reg8[5] at LC5_A21
--operation mode is normal

reg8[5]_lut_out = r8_load & r8_in[5] # !r8_load & (reg8[6]);
reg8[5] = DFFEA(reg8[5]_lut_out, GLOBAL(r8_clk), !GLOBAL(clr), , , , );

--A1L62Q is reg8[5]~41 at LC5_A21
--operation mode is normal

A1L62Q = reg8[5];


--reg8[6] is reg8[6] at LC6_A21
--operation mode is normal

reg8[6]_lut_out = r8_load & r8_in[6] # !r8_load & (reg8[7]);
reg8[6] = DFFEA(reg8[6]_lut_out, GLOBAL(r8_clk), !GLOBAL(clr), , , , );

--A1L82Q is reg8[6]~42 at LC6_A21
--operation mode is normal

A1L82Q = reg8[6];


--reg8[7] is reg8[7] at LC8_A21
--operation mode is normal

reg8[7]_lut_out = r8_in[7];
reg8[7] = DFFEA(reg8[7]_lut_out, GLOBAL(r8_clk), !GLOBAL(clr), , r8_load, , );

--A1L03Q is reg8[7]~43 at LC8_A21
--operation mode is normal

A1L03Q = reg8[7];


--r8_in[0] is r8_in[0] at PIN_54
--operation mode is input

r8_in[0] = INPUT();


--r8_load is r8_load at PIN_124
--operation mode is input

r8_load = INPUT();


--r8_clk is r8_clk at PIN_55
--operation mode is input

r8_clk = INPUT();


--clr is clr at PIN_126
--operation mode is input

clr = INPUT();


--r8_in[1] is r8_in[1] at PIN_56
--operation mode is input

r8_in[1] = INPUT();


--r8_in[2] is r8_in[2] at PIN_125
--operation mode is input

r8_in[2] = INPUT();


--r8_in[3] is r8_in[3] at PIN_100
--operation mode is input

r8_in[3] = INPUT();


--r8_in[4] is r8_in[4] at PIN_102
--operation mode is input

r8_in[4] = INPUT();


--r8_in[5] is r8_in[5] at PIN_7
--operation mode is input

r8_in[5] = INPUT();


--r8_in[6] is r8_in[6] at PIN_101
--operation mode is input

r8_in[6] = INPUT();


--r8_in[7] is r8_in[7] at PIN_44
--operation mode is input

r8_in[7] = INPUT();


--r8_out is r8_out at PIN_8
--operation mode is output

r8_out = OUTPUT(reg8[0]);


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