📄 example 3-7.asm
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;Example 3 - 7. Implementing a Spectrum Analyzer Using a 128-Point FFT and the TMS320F240 EVM
;*****************************************************************************
; File Name: FFT0.ASM
; Project: C240 EVM Test Platform
; Originator: Allister Chang (Texas Instruments)
;
; Description:The program perfoms a 128 point FFT. The data samples
; are gathered from the ADC of the C240. The FFT is performed
; and the magnitudes of the FFT are output via the DAC of the
; EVM test board. The results can then be viewed using
; an oscilloscope. The trigger for the FFT results on the
; oscilloscope is XF.
;
;
;*****************************************************************************
; Last Update:10 June 99
;
; Descriptions: C/F240 on-chip 10bit ADC is connected to the 10 MSB of the
; internal data bus[15:5]. Previous version assumed the ADC
; is connected to the 10 LSB of the data bus. As a result
; all data collected with MSB 1 were interpreted as neg
; number and gave incorrect FFT result.
;
; Status: Works
;
;
;=============================================================================
.include f240regs.h
;-----------------------------------------------------------------------------
; Debug directives
;-----------------------------------------------------------------------------
.defGPR0 ;General purpose registers.
.defGPR1
.defGPR2
.defGPR3
;-----------------------------------------------------------------------------
; FFT specific constants
;-----------------------------------------------------------------------------
N .set128 ;FFT length
TWID_TBL .set08100h ;Start of Twiddle table in B1
B0_SADR .set08000h ;B0 start address (changed to locate data at 0x8000
B0_EADR .set080FFh ;B0 end address
B1_SADR .set08100h ;B1 start address
B1_EADR .set081FFh ;B1 end address
B2_SADR .set0060h ;B2 start address
B2_EADR .set007Fh ;B2 end address
COS45K .set05A82h ;Constant for COS(45)
;---------------------------------------------------------------------
; I/O Mapped EVM Registers
;---------------------------------------------------------------------
DAC0 .set0000h ;Input Data Register for DAC0
DAC1 .set0001h ;Input Data Register for DAC1
DAC2 .set0002h ;Input Data Register for DAC2
DAC3 .set0003h ;Input Data Register for DAC3
DACUPDATE .set0004h ;DAC Update Register
;-----------------------------------------------------------------------------
; Variable Declarations for on chip RAM Block B2 (DP=0)
;-----------------------------------------------------------------------------
.bss GPR0,1 ;General purpose registers.
.bss GPR1,1
.bss GPR2,1
.bss GPR3,1
.bss COS45,1 ;Value for COS(45)
.bss DAC0VAL,1 ;DAC0 Channel Value
.bss DAC1VAL,1 ;DAC1 Channel Value
.bss DAC2VAL,1 ;DAC2 Channel Value
.bss DAC3VAL,1 ;DAC3 Channel Value
.bss COUNTER,1 ;COUNTER for obtaining 128 values
.bss RPT_NUM,1
.bss uSEC,1
;************************************************************************
; *
; MACRO 'ZEROI' number of words/number of cycles: 10 *
; *
; ARP=2 FOR INPUT AND OUTPUT *
; AR2 -> QR,QI,QR+1,... *
; AR1 -> PR,PI,PR+1,... *
; *
; CALCULATE Re[P+Q] AND Re[P-Q] *
; QR'=(PR-QR)/2 *
; PR'=(PR+QR)/2 *
; PI'=(PI+QI)/2 *
; PI'=(PI-QI)/2 *
; *
; version 1.00 from Manfred Christ update: 2. July 90 *
; *
;************************************************************************
ZEROI .macro ; AR1 AR2 ARP
LACC *,15,AR1 ; ACC := (1/2)(QR) PR QR 1
ADD *,15 ; ACC := (1/2)(PR+QR) PR QR 1
SACH *+,0,AR2 ; PR := (1/2)(PR+QR) PI QR 2
SUB *,16 ; ACC := (1/2)(PR+QR)-(QR) PI QR 2
SACH *+ ; QR := (1/2)(PR-QR) PI QI 2
LACC *,15,AR1 ; ACC := (1/2)(QI) PI QI 1
ADD *,15 ; ACC := (1/2)(PI+QI) PI QI 1
SACH *+,0,AR2 ; PI := (1/2)(PI+QI) PR+1 QI 2
SUB *,16 ; ACC := (1/2)(PI+QI)-(QI) PR+1 QI 2
SACH *+ ; QI := (1/2)(PI-QI) PR+1 QR+1 2
.endm
;************************************************************************
; *
; MACRO 'PBY2I' number of words/number of cycles: 12 *
; *
; ARP=2 on entry to macro *
; AR2 -> QR,QI,QR+1,... *
; AR1 -> PR,PI,PR+1,... *
; *
; PR'=(PR+QI)/2 PI'=(PI-QR)/2 *
; QR'=(PR-QI)/2 QI'=(PI+QR)/2 *
; *
; version 1.00 from Manfred Christ update: 02. July 90 *
; *
;************************************************************************
PBY2I .macro ; AR1 AR2 ARP
LACC *+,15,AR5 ; PR QI 5
SACH *,1,AR2 ; TMP=QR PR QI 2
LACC *,15,AR1 ; ACC := QI/2 PR QI 1
ADD *,15 ; ACC := (PR+QI)/2 PR QI 1
SACH *+,0,AR2 ; PR := (PR+QI)/2 PI QI 2
SUB *-,16 ; ACC := (PR-QI)/2 PI QR 2
SACH *+,0,AR1 ; QR := (PR-QI)/2 PI QI 1
LACC *,15,AR5 ; ACC := (PI)/2 PI QI 5
SUB *,15,AR1 ; ACC := (PI-QR)/2 PI QI 1
SACH *+,0,AR5 ; PI := (PI-QR)/2 PR+1 QI 5
ADD *,16,AR2 ; ACC := (PI+QR)/2 PR+1 QI 2
SACH *+ ; QI := (PI+QR)/2 PR+1 QI+1 2
.endm
;************************************************************************
; *
; MACRO 'PBY4I' number of words/number of cycles: 16 *
; *
; T=SIN(45)=COS(45)=W45 *
; *
; PR'= PR + (W*QI + W*QR) = PR + W * QI + W * QR (<- AR1) *
; QR'= PR - (W*QI + W*QR) = PR - W * QI - W * QR (<- AR2) *
; PI'= PI + (W*QI - W*QR) = PI + W * QI - W * QR (<- AR1+1) *
; QI'= PI - (W*QI - W*QR) = PI - W * QI + W * QR (<- AR1+2) *
; *
; *
; version 1.00 from Manfred Christ update: 02. July 90 *
; *
;************************************************************************
PBY4I .macro ; TREG= W AR5 PREG AR1 AR2 ARP
MPY *+,AR5 ; PREG= W*QR/2 - W*QR/2 PR QI 5
SPH *,AR1 ; TMP = W*QR/2 W*QR/2 W*QR/2 PR QI 1
LACC *,15,AR2 ; ACC = PR/2 W*QR/2 W*QR/2 PR QI 2
MPYS *- ; ACC = (PR-W*QR)/2 W*QR/2 W*QI/2 PR QR 2
SPAC ; ACC = (PR-W*QI-W*QR)/2 W*QR/2 W*QI/2 PR QR 2
SACH *+,0,AR1 ; QR = (PR-W*QI-W*QR)/2 W*QR/2 W*QI/2 PR QI 1
SUB *,16 ; ACC = (-PR-W*QI-W*QR)/2 W*QR/2 W*QI/2 PR QI 1
NEG ; ACC = (PR+W*QI+W*QR)/2 W*QR/2 W*QI/2 PR QI 1
SACH *+ ; QR = (PR+W*QI+W*QR)/2 W*QR/2 W*QI/2 PI QI 1
LACC *,15,AR5 ; ACC = (PI)/2 W*QR/2 W*QI/2 PI QI 5
SPAC ; ACC = (PI-W*QI)/2 W*QR/2 - PI QI 5
ADD *,16,AR2 ; ACC = (PI-W*QI+W*QR)/2 - - PI QI 2
SACH *+,0,AR1 ; QI = (PI-W*QI+W*QR)/2 - - PI QR1 1
SUB *,16 ; ACCU= (-PI-W*QI+W*QR)/2 - - PI QR1 1
NEG ; ACCU= (PI+W*QI-W*QR)/2 - - PI QR1 1
SACH *+,0,AR2 ; PI = (PI+W*QI-W*QR)/2 - - PR1 QR1 2
.endm
;************************************************************************
; *
; MACRO 'P3BY4I' number of words/number of cycles: 16 *
; *
; version 1.00 from: Manfred Christ update: 02. July 90 *
; *
; ENTRANCE IN THE MACRO: ARP=AR2 *
; AR1->PR,PI *
; AR2->QR,QI *
; TREG=W=COS(45)=SIN(45) *
; *
; PR'= PR + (W*QI - W*QR) = PR + W * QI - W * QR (<- AR1) *
; QR'= PR - (W*QI - W*QR) = PR - W * QI + W * QR (<- AR2) *
; PI'= PI - (W*QI + W*QR) = PI - W * QI - W * QR (<- AR1+1) *
; QI'= PI + (W*QI + W*QR) = PI + W * QI + W * QR (<- AR1+2) *
; *
; EXIT OF THE MACRO: ARP=AR2 *
; AR1->PR+1,PI+1 *
; AR2->QR+1,QI+1 *
; *
;************************************************************************
P3BY4I .macro p,m ; TREG= W AR5 PREG AR1 AR2 ARP
; ------ ------ --- --- ---
MPY *+,AR5 ; PREG= W*QR/2 - W*QR/2 PR QI 5
SPH *,AR1 ; TMP = W*QR/2 W*QR/2 W*QR/2 PR QI 1
LACC *,15,AR2 ; ACC = PR/2 W*QR/2 W*QR/2 PR QI 2
MPYA *- ; ACC = (PR+W*QR)/2 W*QR/2 W*QI/2 PR QR 2
SPAC ; ACC = (PR-W*QI+W*QR)/2 W*QR/2 W*QI/2 PR QR 2
SACH *+,0,AR1 ; QR' = (PR-W*QI+W*QR)/2 W*QR/2 W*QI/2 PR QI 1
SUB *,16 ; ACC = (-PR-W*QI+W*QR)/2 W*QR/2 W*QI/2 PR QI 1
NEG ; ACC = (PR+W*QI-W*QR)/2 W*QR/2 W*QI/2 PR QI 1
SACH *+ ; PR' = (PR+W*QI-W*QR)/2 W*QR/2 W*QI/2 PI QI 1
LACC *,15,AR5 ; ACC = (PI)/2 W*QR/2 W*QI/2 PI QI 5
APAC ; ACC = (PI+W*QI)/2 W*QR/2 - PI QI 5
ADD *,16,AR2 ; ACC = (PI+W*QI+W*QR)/2 - - PI QI 2
SACH *:m:+,0,AR1 ; QI' = (PI+W*QI+W*QR)/2 - - PI QR5 1
SUB *,16 ; ACCU= (-PI+W*QI+W*QR)/2 - - PI QR5 1
NEG ; ACCU= (PI-W*QI-W*QR)/2 - - PI QR5 1
SACH *:m:+,0,AR:p: ; PI' = (PI-W*QI-W*QR)/2 - PR5 QR5 7
.endm
;********************************************************************************
; *
; MACRO: 'BFLY' general butterfly radix 2 for 320C2xx/5x *
; *
; version 1.00 from Manfred Christ update: 02. July 90 *
; *
; THE MACRO 'BFLY' REQUIRES 18 WORDS AND 18 INSTRUCTIONS *
; *
; Definition: ARP -> AR2 (input) ARP -> AR2 (output) *
; *
; Definition: AR1 -> QR (input) AR1 -> QR+1 (output) *
; Definition: AR2 -> PR (input) AR2 -> PR+1 (output) *
; Definition: AR3 -> Cxxx (input) AR3 -> Cxxx+1 (output) --> WR=cosine *
; Definition: AR4 -> Sxxx (input) AR4 -> Sxxx+1 (output) --> WI=sine *
; Definition: AR5 -> temporary variable (unchanged) *
; *
; uses index register *
; *
; PR' = (PR+(QR*WR+QI*WI))/2 WR=COS(W) WI=SIN(W) *
; PI' = (PI+(QI*WR-QR*WI))/2 *
; QR' = (PR-(QR*WR+QI*WI))/2 *
; QI' = (PI-(QI*WR-QR*WI))/2 *
; *
; Note: AR0 determines Twiddle Pointers (AR3 & AR4) step increments *
; *
;********************************************************************************
BFLY .macro p
; (contents of register after exec.)
; TREG AR1 AR2 AR3 AR4 ARP
; --- --- --- --- --- ---
LT *+,AR3 ;TREG:= QR QR PR QI C S 3
MPY *,AR2 ;PREG:= QR*WR/2 QR PR QI C S 2
LTP *-,AR4 ;ACC := QR*WR/2 QI PR QR C S 4
MPY *,AR3 ;PREG:= QI*WI/2 QI PR QR C S 3
MPYA *0+,AR2 ;ACC := (QR*WR+QI*WI)/2 QR PR QR C+n S 2
;PREG:= QI*WR
LT *,AR5;TREG = QR QR PR QR C+n S 5
SACH *,1,AR1 ;TEMP:= (QR*WR+QI*WI) QR PR QR C+n S 1
ADD *,15 ;ACC := (PR+(QR*WR+QI*WI))/2 QR PR QR C+n S 1
SACH *+,0,AR5 ;PR := (PR+(QR*WR+QI*WI))/2 QR PI QR C+n S 5
SUB *,16,AR2 ;ACC := (PR-(QR*WR+QI*WI))/2 QR PI QR C+n S 2
SACH *+,0,AR1 ;QR := (PR-(QR*WR+QI*WI))/2 QR PI QI C+n S 1
LAC *,15,AR4 ;ACC := PI /PREG=QI*WR QI PI QI C+n S 4
MPYS *0+,AR2 ;PREG:= QR*WI/2 QI PI QI C+n S+n 2
;ACC := (PI-QI*WR)/2
APAC ;ACC := (PI-(QI*WR-QR*WI))/2 QI PI QI C+n S+n 2
SACH *+,0,AR1 ;QI := (PI-(QI*WR-QR*WI))/2 QI PI QR+1 C+n S+n 1
NEG ;ACC :=(-PI+(QI*WR-QR*WI))/2 QI PI QR+1 C+n S+n 1
ADD *,16 ;ACC := (PI+(QI*WR-QR*WI))/2 QI PI QR+1 C+n S+n 1
SACH *+,0,AR:p: ;PI := (PI+(QI*WR-QR*WI))/2 QI PR+1 QR+1 C+n S+n 2
.endm
;******************************************************************************
; MACRO 'COMBO' *
; *
; R1 := [(R1+R2)+(R3+R4)]/4 INPUT OUTPUT *
; R2 := [(R1-R2)+(I3-I4)]/4 ------------------ ------------------ *
; R3 := [(R1+R2)-(R3+R4)]/4 AR0 = 7 *
; R4 := [(R1-R2)-(I3-I4)]/4 AR1 -> R1,I1 AR1 - > R5,I5 *
; I1 := [(I1+I2)+(I3+I4)]/4 AR2 -> R2,I2 AR2 - > R6,I6 *
; I2 := [(I1-I2)-(R3-R4)]/4 ARP -> AR3 -> R3,I3 ARP - > AR3 - > R7,I7 *
; I3 := [(I1+I2)-(I3+I4)]/4 AR4 -> R4,I4 AR4 - > R8,I8 *
; I4 := [(I1-I2)+(R3-R4)]/4 *
; *
;******************************************************************************
; ARP AR1 AR2 AR3 AR4 AR5
COMBO .macro ; --- --- --- --- --- ---
LACC *,14,AR4 ; ACC := (R3)/4 4 R1 R2 R3 R4 T1
SUB *,14,AR5 ; ACC := (R3+R4)/4 5 R1 R2 R3 R4 T1
SACH *+,1,AR4 ; T1 = (R3-R4)/2 4 R1 R2 I3 R4 T2
ADD *+,15,AR5 ; ACC := (R3+R4)/4 5 R1 R2 R3 I4 T2
SACH *,1,AR2 ; T2 = (R3+R4)/2 2 R1 R2 R3 I4 T2
ADD *,14,AR1 ; ACC := (R2+R3+R4)/4 1 R1 R2 R3 I4 T2
ADD *,14 ; ACC := (R1+R2+R3+R4)/4 1 R1 R2 R3 I4 T2
SACH *+,0,AR5 ; R1 := (R1+R2+R3+R4)/4 5 I1 R2 R3 I4 T2
SUB *,16,AR3 ; ACC := (R1+R2-(R3+R4))/4 3 I1 R2 R3 I4 T2
SACH *+,0,AR5 ; R3 := (R1+R2-(R3+R4))/4 5 I1 R2 I3 I4 T2
ADD *,15,AR2 ; ACC := (R1+R2)/4 2 I1 R2 I3 I4 T2
SUB *,15,AR3 ; ACC := (R1-R2)/4 3 I1 R2 I3 I4 T2
ADD *,14,AR4 ; ACC := ((R1-R2)+(I3))/4 4 I1 R2 I3 I4 T2
SUB *,14,AR2 ; ACC := ((R1-R2)+(I3-I4))/4 2 I1 R2 I3 I4 T2
SACH *+,0,AR4 ; R2 := ((R1-R2)+(I3-I4))/4 4 I1 I2 I3 I4 T2
ADD *-,15,AR3 ; ACC := ((R1-R2)+ I3+I4 )/4 3 I1 I2 I3 R4 T2
SUB *,15,AR4 ; ACC := ((R1-R2)-(I3-I4))/4 4 I1 I2 I3 R4 T2
SACH *+,0,AR1 ; R4 := ((R1-R2)-(I3-I4))/4 1 I1 I2 I3 I4 T2
LACC *,14,AR2 ; ACC := (I1)/4 2 I1 I2 I3 I4 T2
SUB *,14,AR5 ; ACC := (I1-I2)/4 5 I1 I2 I3 I4 T2
SACH *,1,AR2 ; T2 := (I1-I2)/2 2 I1 I2 I3 I4 T2
ADD *,15,AR3 ; ACC := ((I1+I2))/4 4 I1 I2 I3 I4 T2
ADD *,14,AR4 ; ACC := ((I1+I2)+(I3))/4 4 I1 I2 I3 I4 T2
ADD *,14,AR1 ; ACC := ((I1+I2)+(I3+I4))/4 1 I1 I2 I3 I4 T2
SACH *0+,0,AR3 ; I1 := ((I1+I2)+(I3+I4))/4 3 R5 I2 I3 I4 T2
SUB *,15,AR4 ; ACC := ((I1+I2)-(I3+I4))/4 4 R5 I2 I3 I4 T2
SUB *,15,AR3 ; ACC := ((I1+I2)-(I3+I4))/4 3 R5 I2 I3 I4 T2
SACH *0+,0,AR5 ; I3 := ((I1+I2)-(I3+I4))/4 5 R5 I2 R7 I4 T2
LACC *-,15 ; ACC := (I1-I2)/4 5 R5 I2 R7 I4 T1
SUB *,15,AR2 ; ACC := ((I1-I2)-(R3-R4))/4 2 R5 I2 R7 I4 T1
SACH *0+,0,AR5 ; I2 := ((I1-I2)-(R3-R4))/4 5 R5 R6 R7 I4 T1
ADD *,16,AR4 ; ACC := ((I1-I2)+(R3-R4))/4 4 R5 R6 R7 I4 T1
SACH *0+,0,AR7; I4 := ((I1-I2)+(R3-R4))/4 7 R5 R6 R7 R8 T1
.endm
;-----------------------------------------------------------------------------
; Vector address declarations
;-----------------------------------------------------------------------------
.sect ".vectors" ; use if Vectors are to be programmed in EPROM
RSVECT B START ; PM 0 Reset Vector 1
INT1 B PHANTOM ; PM 2 Ext Int 1 4
INT2 B PHANTOM ; PM 4 Ext Int 2 5
INT3 B PHANTOM ; PM 6 Ext Int 3 6
INT4 B PHANTOM ; PM 8 Ext Int 4 7
INT5 B PHANTOM ; PM A Ext Int 5 8
INT6 B PHANTOM ; PM C Ext Int 6 9
RESERVED B PHANTOM ; PM E (Analysis Int) 10
SW_INT8 B PHANTOM ; PM 10 User S/W int -
SW_INT9 B PHANTOM ; PM 12 User S/W int -
SW_INT10 B PHANTOM ; PM 14 User S/W int -
SW_INT11 B PHANTOM ; PM 16 User S/W int -
SW_INT12 B PHANTOM ; PM 18 User S/W int -
SW_INT13 B PHANTOM ; PM 1A User S/W int -
SW_INT14 B PHANTOM ; PM 1C User S/W int -
SW_INT15 B PHANTOM ; PM 1E User S/W int -
SW_INT16 B PHANTOM ; PM 20 User S/W int -
TRAP B PHANTOM ; PM 22 Trap vector -
NMINT B PHANTOM ; PM 24 Non maskable Int 3
EMU_TRAP B PHANTOM ; PM 26 Emulator Trap 2
SW_INT20 B PHANTOM ; PM 28 User S/W int -
SW_INT21 B PHANTOM ; PM 2A User S/W int -
SW_INT22 B PHANTOM ; PM 2C User S/W int -
SW_INT23 B PHANTOM ; PM 2E User S/W int -
;==============================================================================
; M A I N C O D E - starts here
;==============================================================================
.text
NOP
START:
SETCINTM ;Disable Interrupts
SPLK #0000h,IMR ;Mask all core interrupts
LACCIFR ;Read Interrupt flags
SACLIFR ;Clear all interrupt flags
NOP
LDP #0h
SPM 0 ;no shift from PREG-->ALU
ROVM ;dis overflow
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