os_cpu_a.lst

这是一个UCOS的AVR移植程序

  85               	\endverbatim
  86               	
  87               	\code
  87               	
  88               	/*
  89               	 * Registers common to all AVR devices.
  90               	 */
  91               	
  92               	#if __AVR_ARCH__ != 1
  93               	/*
  94               	 * AVR architecture 1 has no RAM, thus no stack pointer.
  95               	 *
  96               	 * All other archs do have a stack pointer.  Some devices have only
  97               	 * less than 256 bytes of possible RAM locations (128 Bytes of SRAM
  98               	 * and no option for external RAM), thus SPH is officially "reserved"
  99               	 * for them.  We catch this case below after including the
 100               	 * device-specific ioXXXX.h file, by examining XRAMEND, and
 101               	 * #undef-ining SP and SPH in that case.
 102               	 */
 103               	/* Stack Pointer */
 104               	#define SP        _SFR_IO16(0x3D)
 105               	#define SPL       _SFR_IO8(0x3D)
 106               	#define SPH       _SFR_IO8(0x3E)
 107               	#endif /* #if __AVR_ARCH__ != 1 */
 108               	
 109               	/* Status REGister */
 110               	#define SREG      _SFR_IO8(0x3F)
 111               	
 112               	/* Status Register - SREG */
 113               	#define    SREG_I       7
 114               	#define    SREG_T       6
 115               	#define    SREG_H       5
 116               	#define    SREG_S       4
 117               	#define    SREG_V       3
 118               	#define    SREG_N       2
 119               	#define    SREG_Z       1
 120               	#define    SREG_C       0
 121               	
 122               	/* Pointer definition */
 123               	#if __AVR_ARCH__ != 1
 124               	/* avr1 has only the Z pointer */
 125               	#define    XL           r26
 126               	#define    XH           r27
 127               	#define    YL           r28
 128               	#define    YH           r29
 129               	#endif /* #if __AVR_ARCH__ != 1 */
 130               	#define    ZL           r30
 131               	#define    ZH           r31
 132               	
 133               	/*
 134               	 * Only few devices come without EEPROM.  In order to assemble the
 135               	 * EEPROM library components without defining a specific device, we
 136               	 * keep the EEPROM-related definitions here, and catch the devices
 137               	 * without EEPROM (E2END == 0) below.  Obviously, the EEPROM library
 138               	 * functions will not work for them. ;-)
 139               	 */
 140               	/* EEPROM Control Register */
 141               	#define EECR	_SFR_IO8(0x1C)
 142               	
 143               	/* EEPROM Data Register */
 144               	#define EEDR	_SFR_IO8(0x1D)
 145               	
 146               	/* EEPROM Address Register */
 147               	#define EEAR	_SFR_IO16(0x1E)
 148               	#define EEARL	_SFR_IO8(0x1E)
 149               	#define EEARH	_SFR_IO8(0x1F)
 150               	
 151               	/* EEPROM Control Register */
 152               	#define    EERIE        3
 153               	#define    EEMWE        2
 154               	#define    EEWE         1
 155               	#define    EERE         0
 156               	
 157               	#if defined (__AVR_AT94K__)
 158               	#  include <avr/ioat94k.h>
 159               	#elif defined (__AVR_AT43USB320__)
 160               	#  include <avr/io43u32x.h>
 161               	#elif defined (__AVR_AT43USB355__)
 162               	#  include <avr/io43u35x.h>
 163               	#elif defined (__AVR_AT76C711__)
 164               	#  include <avr/io76c711.h>
 165               	#elif defined (__AVR_AT86RF401__)
 166               	#  include <avr/io86r401.h>
 167               	#elif defined (__AVR_ATmega128__)
 168               	#  include <avr/iom128.h>
 169               	#elif defined (__AVR_AT90CAN128__)
 170               	#  include <avr/iocan128.h>
 171               	#elif defined (__AVR_ATmega64__)
 172               	#  include <avr/iom64.h>
   1               	/* Copyright (c) 2002, Steinar Haugen
   2               	   All rights reserved.
   3               	
   4               	   Redistribution and use in source and binary forms, with or without
   5               	   modification, are permitted provided that the following conditions are met:
   6               	
   7               	   * Redistributions of source code must retain the above copyright
   8               	     notice, this list of conditions and the following disclaimer.
   9               	
  10               	   * Redistributions in binary form must reproduce the above copyright
  11               	     notice, this list of conditions and the following disclaimer in
  12               	     the documentation and/or other materials provided with the
  13               	     distribution.
  14               	
  15               	   * Neither the name of the copyright holders nor the names of
  16               	     contributors may be used to endorse or promote products derived
  17               	     from this software without specific prior written permission.
  18               	
  19               	  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20               	  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21               	  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22               	  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23               	  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24               	  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25               	  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26               	  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27               	  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28               	  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29               	  POSSIBILITY OF SUCH DAMAGE. */
  30               	
  31               	/* $Id: iom64.h,v 1.9 2004/11/02 18:43:56 arcanum Exp $ */
  32               	
  33               	/* avr/iom64.h - defines for ATmega64 
  34               	
  35               	   As of 2002-11-23:
  36               	   - This should be up to date with data sheet Rev. 2490C-AVR-09/02 */
  37               	
  38               	#ifndef _AVR_IOM64_H_
  39               	#define _AVR_IOM64_H_ 1
  40               	
  41               	/* This file should only be included from <avr/io.h>, never directly. */
  42               	
  43               	#ifndef _AVR_IO_H_
  44               	#  error "Include <avr/io.h> instead of this file."
  45               	#endif
  46               	
  47               	#ifndef _AVR_IOXXX_H_
  48               	#  define _AVR_IOXXX_H_ "iom64.h"
  49               	#else
  50               	#  error "Attempt to include more than one <avr/ioXXX.h> file."
  51               	#endif 
  52               	
  53               	/* I/O registers */
  54               	
  55               	/* Input Pins, Port F */
  56               	#define PINF      _SFR_IO8(0x00)
  57               	
  58               	/* Input Pins, Port E */
  59               	#define PINE      _SFR_IO8(0x01)
  60               	
  61               	/* Data Direction Register, Port E */
  62               	#define DDRE      _SFR_IO8(0x02)
  63               	
  64               	/* Data Register, Port E */
  65               	#define PORTE     _SFR_IO8(0x03)
  66               	
  67               	/* ADC Data Register */
  68               	#define ADCW      _SFR_IO16(0x04) /* for backwards compatibility */
  69               	#ifndef __ASSEMBLER__
  70               	#define ADC       _SFR_IO16(0x04)
  71               	#endif
  72               	#define ADCL      _SFR_IO8(0x04)
  73               	#define ADCH      _SFR_IO8(0x05)
  74               	
  75               	/* ADC Control and Status Register A */
  76               	#define ADCSR     _SFR_IO8(0x06) /* for backwards compatibility */
  77               	#define ADCSRA    _SFR_IO8(0x06) 
  78               	
  79               	/* ADC Multiplexer select */
  80               	#define ADMUX     _SFR_IO8(0x07)
  81               	
  82               	/* Analog Comparator Control and Status Register */
  83               	#define ACSR      _SFR_IO8(0x08)
  84               	
  85               	/* USART0 Baud Rate Register Low */
  86               	#define UBRR0L    _SFR_IO8(0x09)
  87               	
  88               	/* USART0 Control and Status Register B */
  89               	#define UCSR0B    _SFR_IO8(0x0A)
  90               	
  91               	/* USART0 Control and Status Register A */
  92               	#define UCSR0A    _SFR_IO8(0x0B)
  93               	
  94               	/* USART0 I/O Data Register */
  95               	#define UDR0      _SFR_IO8(0x0C)
  96               	
  97               	/* SPI Control Register */
  98               	#define SPCR      _SFR_IO8(0x0D)
  99               	
 100               	/* SPI Status Register */
 101               	#define SPSR      _SFR_IO8(0x0E)
 102               	
 103               	/* SPI I/O Data Register */
 104               	#define SPDR      _SFR_IO8(0x0F)
 105               	
 106               	/* Input Pins, Port D */
 107               	#define PIND      _SFR_IO8(0x10)
 108               	
 109               	/* Data Direction Register, Port D */
 110               	#define DDRD      _SFR_IO8(0x11)
 111               	
 112               	/* Data Register, Port D */
 113               	#define PORTD     _SFR_IO8(0x12)
 114               	
 115               	/* Input Pins, Port C */
 116               	#define PINC      _SFR_IO8(0x13)
 117               	
 118               	/* Data Direction Register, Port C */
 119               	#define DDRC      _SFR_IO8(0x14)
 120               	
 121               	/* Data Register, Port C */
 122               	#define PORTC     _SFR_IO8(0x15)
 123               	
 124               	/* Input Pins, Port B */
 125               	#define PINB      _SFR_IO8(0x16)
 126               	
 127               	/* Data Direction Register, Port B */
 128               	#define DDRB      _SFR_IO8(0x17)
 129               	
 130               	/* Data Register, Port B */
 131               	#define PORTB     _SFR_IO8(0x18)
 132               	
 133               	/* Input Pins, Port A */
 134               	#define PINA      _SFR_IO8(0x19)
 135               	
 136               	/* Data Direction Register, Port A */
 137               	#define DDRA      _SFR_IO8(0x1A)
 138               	
 139               	/* Data Register, Port A */
 140               	#define PORTA     _SFR_IO8(0x1B)
 141               	
 142               	/* 0x1C..0x1F EEPROM */
 143               	
 144               	/* Special Function I/O Register */
 145               	#define SFIOR     _SFR_IO8(0x20)
 146               	
 147               	/* Watchdog Timer Control Register */
 148               	#define WDTCR     _SFR_IO8(0x21)
 149