sweep_ech.vhd

频率扫描的VHDL完整代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:47:37 11/28/2011 
-- Design Name: 
-- Module Name:    sweep_ech - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sweep_ech is
 port(clk: in std_logic;
      reset: in std_logic;
		clear: in std_logic;
		sweep_step: in std_logic_vector(23 downto 0);
		DFRE_max_2: in std_logic_vector(23 downto 0);
		acc_E: out std_logic_vector(23 downto 0));
end sweep_ech;

architecture Behavioral of sweep_ech is

signal reset_ech: std_logic;
signal acc_temp: std_logic_vector(24 downto 0);
constant full_one24 :STD_LOGIC_VEctor(23 downto 0):=x"ffffff";
constant full_one23 :STD_LOGIC_VEctor(22 downto 0):="11111111111111111111111";
signal  acc_E_temp: std_logic_vector(23 downto 0);
signal  DFRE_max_2_p: std_logic_vector(23 downto 0);
begin

reset_ech<=reset or clear;
DFRE_max_2_p<=full_one24-DFRE_max_2;

process(clk,reset_ech)
begin
  if reset_ech='1' then
     acc_temp<=(others=>'0');
  elsif rising_edge(clk) then
     acc_temp<=acc_temp+sweep_step;
  end if;
end process;

process(clk)
 begin 
   if rising_edge(clk) then
	   if acc_temp(24 downto 23)="00" then
		   acc_E_temp<=acc_temp(23 downto 0);
		elsif acc_temp(24 downto 23)="01" then
		   acc_E_temp(23)<='0';
		   acc_E_temp(22 downto 0)<=full_one23-acc_temp(22 downto 0);
		elsif acc_temp(24 downto 23)="10" then
		   acc_E_temp(23)<='1';
		   acc_E_temp(22 downto 0)<=full_one23-acc_temp(22 downto 0);
		elsif acc_temp(24 downto 23)="11" then
		   acc_E_temp(23)<='1';
			acc_E_temp(22 downto 0)<=acc_temp(22 downto 0);
		else
		  acc_E<=x"000000"; 
		end if;
   end if;
end process;

process(clk)
begin
 if rising_edge(clk) then
    if acc_E_temp(23)='0' then
	    if acc_E>=DFRE_max_2 then
		    acc_E<=DFRE_max_2;
		 else
		    acc_E<=acc_E_temp;
		 end if;
	 else
	    if acc_E>=DFRE_max_2_p then
		    acc_E<=acc_E_temp;
		 else
		     acc_E<=DFRE_max_2;
	    end if;
    end if;
 end if;
end process;

end Behavioral;