fs_top.vhd

频率扫描的VHDL完整代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:33:13 11/28/2011 
-- Design Name: 
-- Module Name:    FS_Top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FS_Top is
    Port ( clk        : in  STD_LOGIC;
           reset      : in  STD_LOGIC;
           IF_center  : in  STD_LOGIC_VECTOR (47 downto 0);
			  Mod_sel    : in  std_logic_vector (7 downto 0);
           DFRE_max_1 : in  STD_LOGIC_VECTOR (23 downto 0);
			  DFRE_max_2 : in  STD_LOGIC_VECTOR (23 downto 0);
           Sweep_step : in  STD_LOGIC_VECTOR (23 downto 0);
			  Sweep_N    : in  std_logic_vector (7  downto 0);
			  IF_out     : out STD_LOGIC_VECTOR (47 downto 0);
			  Sweep_stop : out std_logic);
end FS_Top;

architecture Behavioral of FS_Top is

signal Acc_T :std_logic_vector(23 downto 0);
signal Acc_E :std_logic_vector(23 downto 0);
signal Acc_S :std_logic_vector(23 downto 0);
signal Acc_new :std_logic_vector(23 downto 0);
signal Acc_old :std_logic_vector(23 downto 0);
signal fre_d : std_logic_vector(47 downto 0);
signal counter: std_logic_vector(15 downto 0);
signal clear_T: std_logic;
signal clear_E: std_logic;
signal clear_S: std_logic;

component sweep_tri is 
 port(clk: in std_logic;
      reset: in std_logic;
		clear: in std_logic;
		sweep_step: in std_logic_vector(23 downto 0);
		acc_T: out std_logic_vector(23 downto 0));
end component;

component sweep_ech is
 port(clk: in std_logic;
      reset: in std_logic;
		clear: in std_logic;
		sweep_step: in std_logic_vector(23 downto 0);
		DFRE_max_2: in std_logic_vector(23 downto 0);
		acc_E: out std_logic_vector(23 downto 0));
end component;

component sweep_sine is 
  port(clk: in std_logic;
       reset: in std_logic;
		 clear: in std_logic;
		 sweep_step: in std_logic_vector(23 downto 0);
		 acc_S: out std_logic_vector(23 downto 0));
end component;

component mul_sweep is 
  port(clk :in std_logic;
       a   : in std_logic_vector(23 downto 0);
		 b   :in std_logic_vector(23 downto 0);
		 p   : out std_logic_vector(47 downto 0));
end component;  
begin

u_tri: sweep_tri port map 
     (clk=>clk,
      reset=>reset,
	   clear=>clear_T,
		sweep_step=>sweep_step,
		acc_T=>acc_T);


u_ech: sweep_ech port map 
     (clk=>clk,
      reset=>reset,
		sweep_step=>sweep_step,
		DFRE_max_2=>DFRE_max_2,
		clear=>clear_E,
		acc_E=>acc_E);


u_sine: sweep_sine port map 
     (clk=>clk,
      reset=>reset,
		sweep_step=>sweep_step,
		clear=>clear_S,
		acc_S=>acc_S);

process(clk,reset)
begin
if reset='1' then
   counter<=x"0001";
elsif rising_edge(clk) then
     case  mod_sel is
	  when  x"01" =>
	      Acc_new<=acc_T;
			clear_T<='0';
			clear_E<='1';
			clear_S<='1';
	  when  x"02" =>
	      Acc_new<=acc_E;
			clear_T<='1';
			clear_E<='1';
			clear_S<='0';
	  when  x"04" =>
	      Acc_new<=acc_S;
			clear_T<='1';
			clear_E<='1';
			clear_S<='0';
	  when others   =>
	      Acc_new<=x"000000";
			clear_T<='1';
			clear_E<='1';
			clear_S<='1';
	  end case;
         Acc_old<=Acc_new;
     if  Acc_old(23)='1' and Acc_new(23)='0' then
	     if counter=Sweep_N then
		     counter<=x"0001";
			  Sweep_stop<='1';
		  else
		     Sweep_stop<='0';
		     counter<=counter+'1';
		  end if;
	  else
	     Sweep_stop<='0';
		  counter<=counter;
	  end if;
end if;
end process;                                                 --扫频起始

u_mul:mul_sweep port map  (clk=>clk,a=>Acc_new,b=>DFRE_max_1,p=>fre_d);

process(clk,reset)
begin
  if reset='1' then
     IF_out<=x"000000000000";
  elsif rising_edge (clk) then
     IF_out<=IF_center+fre_d;
  end if;
end process;

end Behavioral;