sweep_sine.vhd

频率扫描的VHDL完整代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:47:51 11/28/2011 
-- Design Name: 
-- Module Name:    sweep_sine - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sweep_sine is
port(clk: in std_logic;
       reset: in std_logic;
		 clear: in std_logic;
		 sweep_step: in std_logic_vector(23 downto 0);
		 acc_S: out std_logic_vector(23 downto 0));
end sweep_sine;

architecture Behavioral of sweep_sine is

signal reset_tri: std_logic;

begin

reset_tri<=reset or clear;




end Behavioral;