modelsim.ini

频率扫描的VHDL完整代码

;    -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1

; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1

; Turns on lint-style checking.
; Show_Lint = 1

; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1

; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile = 1;

; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1

; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1

; Run the 0-in compiler on the VHDL source files
; Default is off.
; ZeroIn = 1

; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""

; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft

; Turn off code coverage in VHDL subprograms. Default is on.
; CoverageSub = 0

; Automatically exclude VHDL case statement OTHERS choice branches.
; This includes OTHERS choices in selected signal assigment statements.
; Default is to not exclude.
; CoverExcludeDefault = 1

; Control compiler and VOPT optimizations that are allowed when
; code coverage is on.  Refer to the comment for this in the [vlog] area. 
; CoverOpt = 3

; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0

; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192

; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192

; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0

; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0

; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp

; Set this to cause the compilers to force data to be committed to disk
; when the files are closed.
; SyncCompilerFiles = 1

; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1

; Range and length checking will be performed on array indices and discrete
; ranges, and when violations are found within subprograms, errors will be
; reported. Default is to issue warnings for violations, because subprograms
; may not be invoked.
; NoDeferSubpgmCheck = 0

; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0

; Turn off reset state transitions in FSM.
; FsmResetTrans = 0

; Do not show immediate assertions with constant expressions in 
; GUI/report/UCDB etc. By default immediate assertions with constant 
; expressions are shown in GUI/report/UCDB etc. This does not affect ;
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0 

[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1

; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1

; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1

; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1

; Turns on lint-style checking.
; Show_Lint = 1

; Show source line containing error. Default is off.
; Show_source = 1

; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1

; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
; vlog95compat = 1

; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0

; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M.  (i.e. memories with depth equal
; to or greater than 1M are marked as sparse)
; SparseMemThreshold = 1048576 

; Run the 0-in compiler on the Verilog source files
; Default is off.
; ZeroIn = 1

; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""

; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1

; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft

; Automatically exclude Verilog case statement default branches. 
; Default is to not automatically exclude defaults.
; CoverExcludeDefault = 1

; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a Verilog condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192

; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192

; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0

; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0


; Turn on code coverage in VLOG `celldefine modules and modules included
; using vlog -v and -y. Default is off.
; CoverCells = 1

; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 1 to 4, with the following
; meanings (the default is 3):
;    1 -- Turn off all optimizations that affect coverage reports.
;    2 -- Allow optimizations that allow large performance improvements 
;         by invoking sequential processes only when the data changes. 
;         This may make major reductions in coverage counts.
;    3 -- In addition, allow optimizations that may change expressions or 
;         remove some statements. Allow constant propagation. Allow VHDL
;         subprogram inlining and VHDL FF recognition. 
;    4 -- In addition, allow optimizations that may remove major regions of 
;         code by changing assignments to built-ins or removing unused
;         signals. Change Verilog gates to continuous assignments.
; CoverOpt = 3

; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0

; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0

; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with 
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
;    variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr

; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; in the [vsim] section can override this value.
; SVCovergroupGoalDefault = 100

; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; in the [vsim] section can override this value.
; SVCovergroupTypeGoalDefault = 100

; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
; SVCovergroupStrobeDefault = 0

; Specify the override for the default value of "merge_instances" option for
; the Covergroup Type. This is a compile time option which forces 
; "merge_instances" to a user specified default value and supersedes 
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupMergeInstancesDefault = 0

; Specify the override for the default value of "per_instance" option for the
; Covergroup variables. This is a compile time option which forces "per_instance"
; to a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero).
; SVCovergroupPerInstanceDefault = 0

; Specify the override for the default value of "get_inst_coverage" option for the
; Covergroup variables. This is a compile time option which forces 
; "get_inst_coverage" to a user specified default value and supersedes 
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupGetInstCoverageDefault = 0