📄 dcf_api.c
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pNim->scan_direction = DCF_SCANUP;
/* set sweep rate. sweep rate = 1000* (sweep rate (in MHz/s) / symbol rate (in MBaud/s) */
switch(pNim->mod_type)
{
case DCF_MOD_QAM16 :
case DCF_MOD_QAM32 :
case DCF_MOD_QAM64 :
pNim->sweep_rate = DCF_FAST_SWEEP_SPEED;
break;
case DCF_MOD_QAM128 :
case DCF_MOD_QAM256 :
pNim->sweep_rate = DCF_SLOW_SWEEP_SPEED;
break;
default:
pNim->sweep_rate = DCF_FAST_SWEEP_SPEED;
break;
}
/* for low SR, we MUST divide Sweep by 2 */
if (pNim->symbol_rate_ideal <= DCF_SYMBOLRATE_LEVEL)
{
pNim->sweep_rate /= 2;
}
/* carrier offset */
pNim->freq_offset = DCF_CARRIER_OFFSET_RATIO * 100; /* in % */
/*debug_out(TL_ALWAYS, "dcf_init_acq: sweep_rate=%d, freq_offset=%d\n", pNim->sweep_rate, pNim->freq_offset);*/
/* set acquisition direction */
if(pNim->scan_direction == DCF_SCANUP)
{
pNim->freq_offset *= -1;
pNim->sweep_rate *= 1;
}
else
{
pNim->freq_offset *= 1;
pNim->sweep_rate *= -1;
}
return(False);
}
bool dcf_set_crl_timeout(DCF_NIM *pNim, long *pn32LMSTimeout, long *pn32FECTimeout)
{
long n32NbSymbols;
long n32Log2QAMSize;
long n32AcqLoopsTime;
/* sanity check */
if(pNim == NULL)
return(False);
/* AcqLoopsTime (in mSec ) : it is the time required for the
lock of the carrier and timing loops */
switch(pNim->mod_type)
{
case DCF_MOD_QAM16:
n32Log2QAMSize = 4;
break;
case DCF_MOD_QAM32:
n32Log2QAMSize = 5;
break;
case DCF_MOD_QAM64:
n32Log2QAMSize = 6;
break;
case DCF_MOD_QAM128:
n32Log2QAMSize = 7;
break;
case DCF_MOD_QAM256:
n32Log2QAMSize = 8;
break;
default:
n32Log2QAMSize = 6;
}
n32NbSymbols = 100000; /* 100000 symbols */
/* divider check */
if(pNim->symbol_rate_ideal == 0)
return(False);
n32AcqLoopsTime = n32NbSymbols/(pNim->symbol_rate_ideal / 1000);
/*
SweepRate = 1000*(Sweep Rate/Symbol Rate)
CarrierOffset = 10000 * (Offset/Symbol Rate)
then :
LMS2TimeOut = 100 * (CarrierOffset/SweepRate)
In order to scan [-Offset, +Offset], we must double LMS2TimeOut.
In order to be safe, 25% margin is added
*/
if(pNim->sweep_rate != 0)
{
*pn32LMSTimeout = 250L*(pNim->freq_offset);
if(pNim->sweep_rate == 0)
return(False);
*pn32LMSTimeout /= (pNim->sweep_rate); /* in ms */
if (*pn32LMSTimeout < 0)
*pn32LMSTimeout = - (*pn32LMSTimeout);
}
else
{
*pn32LMSTimeout = 0;
}
/* The equalizer timeout must be greater than the carrier and timing lock time */
*pn32LMSTimeout += n32AcqLoopsTime;
/* even in case of low carrier offset, LMS2TimeOut will not be lower than a min
which is linked with the QAM size. */
switch(pNim->mod_type)
{
case DCF_MOD_QAM16:
case DCF_MOD_QAM32:
case DCF_MOD_QAM64:
if(*pn32LMSTimeout < 100)
*pn32LMSTimeout = 100;
break;
case DCF_MOD_QAM128:
case DCF_MOD_QAM256:
case DCF_MOD_QAMAUTO:
if(*pn32LMSTimeout < 200)
*pn32LMSTimeout = 200;
break;
}
/* FECTimeOut (in mSec) : it is the time necessary for the FEC to lock in the worst case. */
/* divider check */
if(n32Log2QAMSize == 0)
return(False);
*pn32FECTimeout = ((17+16)*(204*8))/(n32Log2QAMSize*(pNim->symbol_rate_ideal / 1000)); /* in mSec */
*pn32FECTimeout += 10;
return(True);
}
/*****************************************************************************/
/* FUNCTION: dcf_set_dampling_factor */
/* */
/* PARAMETERS: pNim - pointer to DCF_NIM struct. */
/* */
/* DESCRIPTION: The function sets dampling factor. */
/* */
/* RETURNS: True if successful, False if unsuccessful. */
/* */
/* CONTEXT: Must be called from a non-interrupt context. */
/* */
/*****************************************************************************/
bool dcf_set_dampling_factor(DCF_NIM *pNim)
{
unsigned char u8RegData;
bool bRetVal;
unsigned char u8DamplingFactor;
/* For low SR, we MUST Change Dampling Factor 4..8 to 4..A */
if(pNim->symbol_rate_ideal < DCF_SYMBOLRATE_LEVEL)
{
/* Pass Dampling factor to 4..8/9/10 */
switch(pNim->mod_type)
{
case DCF_MOD_QAM16:
case DCF_MOD_QAM32:
case DCF_MOD_QAM64:
default:
u8DamplingFactor = 0x49;
break;
case DCF_MOD_QAM128:
case DCF_MOD_QAM256:
case DCF_MOD_QAMAUTO:
u8DamplingFactor = 0x4A;
break;
}
}
else
{
/* Pass Dampling factor to 4..8/9/10 */
switch (pNim->mod_type)
{
case DCF_MOD_QAM16:
case DCF_MOD_QAM32:
case DCF_MOD_QAM64:
default:
u8DamplingFactor = 0x48;
break;
case DCF_MOD_QAM128:
case DCF_MOD_QAM256:
case DCF_MOD_QAMAUTO:
u8DamplingFactor = 0x49;
break;
}
}
/* 0x61[6:0] */
gDemReg[ST0_RID_CRL_1].value &= 0x80;
gDemReg[ST0_RID_CRL_1].value |= u8DamplingFactor;
u8RegData = gDemReg[ST0_RID_CRL_1].value;
bRetVal= DCF_RegWrite(pNim, gDemReg[ST0_RID_CRL_1].addr, 1, &u8RegData, DCF_DEMOD_I2C);
return(bRetVal);
}
/*****************************************************************************/
/* FUNCTION: dcf_demod_setting */
/* */
/* PARAMETERS: pNim - pointer to DCF_NIM struct. */
/* */
/* DESCRIPTION: The function deos some demod settings. */
/* */
/* RETURNS: True if successful, False if unsuccessful. */
/* */
/* CONTEXT: Must be called from a non-interrupt context. */
/* */
/*****************************************************************************/
bool dcf_demod_setting(DCF_NIM *pNim)
{
long n32Tmp;
unsigned char *pu8Tabi,*pu8Tabt;
unsigned char u8RegIndex, u8RegData;
bool bRetVal;
/* initial demodulator setting : init freq = IF + Offset - Fclock */
n32Tmp = pNim->tuner.tua6020.tuner_interm_freq + pNim->init_demod_offset; /* in KHz */
n32Tmp -= pNim->demod_xtal; /* in KHz */
n32Tmp *= 65536;
if(pNim->demod_xtal == 0)
return(False);
n32Tmp /= pNim->demod_xtal;
if(n32Tmp > 65535)
n32Tmp = 65535 ;
/*debug_out(TL_ALWAYS, "dcf_demod_setting: init_demod_offset=%X\n", n32Tmp);*/
u8RegData = (n32Tmp & 0xFF);
bRetVal= DCF_RegWrite(pNim, gDemReg[ST0_RID_INITDEM_0].addr, 1, &u8RegData, DCF_DEMOD_I2C);
if(bRetVal == False)
return(False);
u8RegData = ((n32Tmp >> 8) & 0xFF);
bRetVal= DCF_RegWrite(pNim, gDemReg[ST0_RID_INITDEM_1].addr, 1, &u8RegData, DCF_DEMOD_I2C);
if(bRetVal == False)
return(False);
/* set registers */
switch(pNim->mod_type)
{
case DCF_MOD_QAM16 :
pu8Tabi = (unsigned char*)&gu8QAM16[0];
pu8Tabt = (unsigned char*)&gu8QAM16_DCF8720[0];
break;
case DCF_MOD_QAM32 :
pu8Tabi = (unsigned char*)&gu8QAM32[0];
pu8Tabt = (unsigned char*)&gu8QAM32_DCF8720[0];
break;
case DCF_MOD_QAM64 :
pu8Tabi = (unsigned char*)&gu8QAM64[0];
pu8Tabt = (unsigned char*)&gu8QAM64_DCF8720[0];
break;
case DCF_MOD_QAM128 :
pu8Tabi = (unsigned char*)&gu8QAM128[0];
pu8Tabt = (unsigned char*)&gu8QAM128_DCF8720[0];
break;
case DCF_MOD_QAM256 :
pu8Tabi = (unsigned char*)&gu8QAM256[0];
pu8Tabt = (unsigned char*)&gu8QAM256_DCF8720[0];
break;
case DCF_MOD_QAMAUTO:
pu8Tabi = (unsigned char*)&gu8QAMAUTO[0];
pu8Tabt = (unsigned char*)&gu8QAMAUTO_DCF8720[0];
break;
default:
pu8Tabi = NULL;
break;
}
if(pu8Tabi != NULL)
{
/* Write to registers */
do
{
u8RegIndex = *pu8Tabi++;
u8RegData = *pu8Tabi++;
bRetVal= DCF_RegWrite(pNim, gDemReg[u8RegIndex].addr, 1, &u8RegData, DCF_DEMOD_I2C);
if(bRetVal == False)
return(False);
}
while(*pu8Tabi!=0);
}
if(pu8Tabt != NULL)
{
/* Write to registers */
do
{
u8RegIndex = *pu8Tabt++;
u8RegData = *pu8Tabt++;
bRetVal= DCF_RegWrite(pNim, gDemReg[u8RegIndex].addr, 1, &u8RegData, DCF_DEMOD_I2C);
if(bRetVal == False)
return(False);
}
while(*pu8Tabt!=0);
}
/* enable init demod */
gDemReg[ST0_RID_INITDEM_5].value = 0x80;
u8RegData = gDemReg[ST0_RID_INITDEM_5].value;
bRetVal= DCF_RegWrite(pNim, gDemReg[ST0_RID_INITDEM_5].addr, 1, &u8RegData, DCF_DEMOD_I2C);
if(bRetVal == False)
return(False);
/* source selection : internal A/D 0x87[7] = 0 */
u8RegData = gDemReg[ST0_RID_CTRL_7].value & 0x7F;
bRetVal= DCF_RegWrite(pNim, gDemReg[ST0_RID_CTRL_7].addr, 1, &u8RegData, DCF_DEMOD_I2C);
if(bRetVal == False)
return(False);
return(True);
}
/*****************************************************************************/
/* FUNCTION: dcf_data_search */
/* */
/* PARAMETERS: pNim - pointer to DCF_NIM struct. */
/* pTsOutFormat - pointer to OUTFORMAT struct */
/* */
/* DESCRIPTION: The function re-initializes THOMSON Cable Front-End DCF8722 */
/* */
/* RETURNS: True if successful, False if unsuccessful. */
/* */
/* CONTEXT: Must be called from a non-interrupt context. */
/* */
/*****************************************************************************/
bool dcf_data_search(DCF_NIM *pNim)
{
long n32LMS2TimeOut;
long n32FECTimeOut;
long n32TimeOut;
int n32LockCounter;
long n32DataSearchTime;
int n32Tmp;
int n32AGC1Max, n32AGC1Min;
int n32AGC2Max, n32AGC2Min;
int n32AGC2SD;
int n32WBAGC_Iref;
int n32AGC2Threshold;
bool bEndOfSearch;
unsigned char u8RegData;
bool bRetVal;
bool bLocked;
/* Initialize parameters */
bEndOfSearch = False;
n32DataSearchTime = 0;
/*debug_out(TL_ALWAYS, "dcf_data_search: FREQ=%d SR=%d MOD=%d\n", pNim->freq_ideal, pNim->symbol_rate_ideal, pNim->mod_type);*/
/* set LMS2 time out and FEC time out */
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